Searched refs:SrcClockDomain (Results 1 - 25 of 59) sorted by relevance

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/gem5/src/sim/
H A DDVFSHandler.py44 # and manages all the source clock domains (SrcClockDomain) it is configured to
53 domains = VectorParam.SrcClockDomain([], "list of domains")
56 sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain,
H A Dclock_domain.cc54 #include "params/SrcClockDomain.hh"
80 SrcClockDomain::SrcClockDomain(const Params *p) : function in class:SrcClockDomain
115 SrcClockDomain::clockPeriod(Tick clock_period)
139 SrcClockDomain::perfLevel(PerfLevel perf_level)
157 void SrcClockDomain::signalPerfLevelUpdate()
168 SrcClockDomain::serialize(CheckpointOut &cp) const
175 SrcClockDomain::unserialize(CheckpointIn &cp)
182 SrcClockDomain::startup()
189 SrcClockDomain *
[all...]
H A Dvoltage_domain.hh63 typedef SrcClockDomain::PerfLevel PerfLevel;
102 * Register a SrcClockDomain with this voltage domain.
103 * @param src_clock_domain The SrcClockDomain to register.
105 void registerSrcClockDom(SrcClockDomain *src_clock_dom) {
155 typedef std::vector<SrcClockDomain *> SrcClockChildren;
H A Ddvfs_handler.hh77 typedef SrcClockDomain::DomainID DomainID;
78 typedef SrcClockDomain::PerfLevel PerfLevel;
137 SrcClockDomain *d = findDomain(domain_id);
144 "SrcClockDomain %s. Returning 0\n", name(), perf_level, d->name());
181 typedef std::map<DomainID, SrcClockDomain*> Domains;
192 SrcClockDomain* sysClkDomain;
200 SrcClockDomain *findDomain(DomainID domain_id) const {
H A DClockDomain.py52 class SrcClockDomain(ClockDomain): class in inherits:ClockDomain
53 type = 'SrcClockDomain'
H A Dclock_domain.hh57 #include "params/SrcClockDomain.hh"
171 class SrcClockDomain : public ClockDomain class in inherits:ClockDomain
177 SrcClockDomain(const Params *p);
/gem5/tests/configs/
H A Do3-timing-ruby.py41 clk_domain = SrcClockDomain(clock = '1GHz'))
45 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
H A Dtwosys-tsunami-simple-atomic.py42 test_sys.clk_domain = SrcClockDomain(clock = '1GHz',
52 test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
57 test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
77 drive_sys.clk_domain = SrcClockDomain(clock = '1GHz',
87 drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz',
92 drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
H A Do3-timing-mp-ruby.py41 clk_domain = SrcClockDomain(clock = '1GHz'))
45 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
H A Dsimple-atomic-mp-ruby.py40 clk_domain = SrcClockDomain(clock = '1GHz'))
44 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
H A Dt1000-simple-atomic.py40 system.clk_domain = SrcClockDomain(clock = '1GHz',
42 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
H A Dsimple-timing-ruby.py68 system.clk_domain = SrcClockDomain(clock = '1GHz',
73 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
80 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Dsimple-timing-mp-ruby.py68 system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
72 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
77 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
H A Dmemtest-ruby.py78 system.clk_domain = SrcClockDomain(clock = '1GHz',
83 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
95 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Dmemtest.py44 system.clk_domain = SrcClockDomain(clock = '1GHz',
49 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
H A Dmemtest-filter.py44 system.clk_domain = SrcClockDomain(clock = '1GHz',
49 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
H A Dpc-simple-timing-ruby.py62 system.clk_domain = SrcClockDomain(clock = '1GHz',
64 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
72 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Dtgen-simple-mem.py54 clk_domain = SrcClockDomain(clock = '1GHz',
H A Dtgen-dram-ctrl.py54 clk_domain = SrcClockDomain(clock = '1GHz',
/gem5/tests/gem5/memory/
H A Dmemtest-run.py45 system.clk_domain = SrcClockDomain(clock = '1GHz',
50 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
/gem5/util/tlm/conf/
H A Dtlm_master.py58 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
H A Dtlm_slave.py60 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
H A Dtlm_elastic_slave.py80 system.clk_domain = SrcClockDomain(clock = '1GHz',
88 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
/gem5/configs/learning_gem5/part3/
H A Druby_test.py51 system.clk_domain = SrcClockDomain()
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py87 system.clk_domain = SrcClockDomain(clock = '1GHz',
95 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',

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