1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../../../configs/') 32from common.Caches import * 33 34#MAX CORES IS 8 with the fals sharing method 35nb_cores = 8 36cpus = [MemTest(max_loads = 1e5, progress_interval = 1e4) 37 for i in xrange(nb_cores) ] 38 39# system simulated 40system = System(cpu = cpus, 41 physmem = SimpleMemory(), 42 membus = SystemXBar()) 43# Dummy voltage domain for all our clock domains 44system.voltage_domain = VoltageDomain() 45system.clk_domain = SrcClockDomain(clock = '1GHz', 46 voltage_domain = system.voltage_domain) 47 48# Create a seperate clock domain for components that should run at 49# CPUs frequency 50system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 51 voltage_domain = system.voltage_domain) 52 53system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) 54system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 55system.l2c.cpu_side = system.toL2Bus.master 56 57# connect l2c to membus 58system.l2c.mem_side = system.membus.slave 59 60# add L1 caches 61for cpu in cpus: 62 # All cpus are associated with cpu_clk_domain 63 cpu.clk_domain = system.cpu_clk_domain 64 cpu.l1c = L1Cache(size = '32kB', assoc = 4) 65 cpu.l1c.cpu_side = cpu.port 66 cpu.l1c.mem_side = system.toL2Bus.slave 67 68system.system_port = system.membus.slave 69 70# connect memory to membus 71system.physmem.port = system.membus.master 72 73 74# ----------------------- 75# run simulation 76# ----------------------- 77 78root = Root( full_system = False, system = system ) 79root.system.mem_mode = 'timing' 80 81m5.instantiate() 82exit_event = m5.simulate() 83if exit_event.getCause() != "maximum number of loads reached": 84 exit(1) 85 86