1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31
32nb_cores = 4
33cpus = [ AtomicSimpleCPU(cpu_id=i) for i in range(nb_cores) ]
34
35import ruby_config
36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
37
38# system simulated
39system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
40                clk_domain = SrcClockDomain(clock = '1GHz'))
41
42# Create a seperate clock domain for components that should run at
43# CPUs frequency
44system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
45
46# add L1 caches
47for cpu in cpus:
48    cpu.connectAllPorts(system.membus)
49    # All cpus are associated with cpu_clk_domain
50    cpu.clk_domain = system.cpu_clk_domain
51
52# connect memory to membus
53system.physmem.port = system.membus.master
54
55# Connect the system port for loading of binaries etc
56system.system_port = system.membus.slave
57
58# -----------------------
59# run simulation
60# -----------------------
61
62root = Root(full_system = False, system = system)
63root.system.mem_mode = 'atomic'
64