1# Copyright (c) 2016, University of Kaiserslautern
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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9#    this list of conditions and the following disclaimer.
10#
11# 2. Redistributions in binary form must reproduce the above copyright
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17#    this software without specific prior written permission.
18#
19# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
23# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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28# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30#
31# Authors: Matthias Jung
32
33import m5
34import optparse
35
36from m5.objects import *
37from m5.util import addToPath, fatal
38
39addToPath('../../../configs/common/')
40
41from Caches import *
42
43# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
44# and an external TLM port for SystemC co-simulation.
45#
46# We assume a DRAM size of 512MB and L1 cache sizes of 32KB and an L2 cache
47# size of 1MB.
48#
49# Base System Architecture:
50#
51#                  +-----------+       ^
52# +-------------+  | eTraceCPU |       |
53# | System Port |  +-----+-----+       |
54# +------+------+  | $D1 | $I1 |       |
55#        |         +--+--+--+--+       |
56#        |            |     |          | gem5 World (see this file)
57#        |         +--v-----v--+       |
58#        |         | toL2Bus   |       |
59#        |         +-----+-----+       |
60#        |               |             |
61#        |         +-----v-----+       |
62#        |         |    L2     |       |
63#        |         +-----+-----+       |
64#        |               |             |
65# +------v---------------v-----+       |
66# |           Membus           |       v
67# +----------------+-----------+       External Port (see sc_port.*)
68#                  |                   ^
69#              +---v---+               | TLM World
70#              |  TLM  |               | (see sc_target.*)
71#              +-------+               v
72#
73#
74# Create a system with a Crossbar and an Elastic Trace Player as CPU:
75
76# Setup System:
77system = System(cpu=TraceCPU(cpu_id=0),
78                mem_mode='timing',
79                mem_ranges = [AddrRange('1024MB')],
80                cache_line_size = 64)
81
82# Create a top-level voltage domain:
83system.voltage_domain = VoltageDomain()
84
85# Create a source clock for the system. This is used as the clock period for
86# xbar and memory:
87system.clk_domain = SrcClockDomain(clock =  '1GHz',
88        voltage_domain = system.voltage_domain)
89
90# Create a CPU voltage domain:
91system.cpu_voltage_domain = VoltageDomain()
92
93# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
94# is actually used only by the caches connected to the CPU:
95system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
96        voltage_domain = system.cpu_voltage_domain)
97
98# Setup CPU and its L1 caches:
99system.cpu.createInterruptController()
100system.cpu.icache = L1_ICache(size="32kB")
101system.cpu.dcache = L1_DCache(size="32kB")
102system.cpu.icache.cpu_side = system.cpu.icache_port
103system.cpu.dcache.cpu_side = system.cpu.dcache_port
104
105# Assign input trace files to the eTraceCPU:
106system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
107system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
108
109# Setting up L1 BUS:
110system.tol2bus = L2XBar()
111system.l2cache = L2Cache(size="1MB")
112system.physmem = SimpleMemory() # This must be instantiated, even if not needed
113
114# Create a external TLM port:
115system.tlm = ExternalSlave()
116system.tlm.addr_ranges = [AddrRange('4096MB')]
117system.tlm.port_type = "tlm_slave"
118system.tlm.port_data = "transactor1"
119
120# Connect everything:
121system.membus = SystemXBar()
122system.system_port = system.membus.slave
123system.cpu.icache.mem_side = system.tol2bus.slave
124system.cpu.dcache.mem_side = system.tol2bus.slave
125system.tol2bus.master = system.l2cache.cpu_side
126system.l2cache.mem_side = system.membus.slave
127system.membus.master = system.tlm.port
128
129# Start the simulation:
130root = Root(full_system = False, system = system)
131root.system.mem_mode = 'timing'
132m5.instantiate()
133m5.simulate() # Simulation time specified later on commandline
134