13691Shsul@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan 23691Shsul@eecs.umich.edu# All rights reserved. 33691Shsul@eecs.umich.edu# 43691Shsul@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 53691Shsul@eecs.umich.edu# modification, are permitted provided that the following conditions are 63691Shsul@eecs.umich.edu# met: redistributions of source code must retain the above copyright 73691Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 83691Shsul@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 93691Shsul@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 103691Shsul@eecs.umich.edu# documentation and/or other materials provided with the distribution; 113691Shsul@eecs.umich.edu# neither the name of the copyright holders nor the names of its 123691Shsul@eecs.umich.edu# contributors may be used to endorse or promote products derived from 133691Shsul@eecs.umich.edu# this software without specific prior written permission. 143691Shsul@eecs.umich.edu# 153691Shsul@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163691Shsul@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173691Shsul@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183691Shsul@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193691Shsul@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203691Shsul@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213691Shsul@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223691Shsul@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233691Shsul@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243691Shsul@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253691Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263691Shsul@eecs.umich.edu# 273691Shsul@eecs.umich.edu# Authors: Lisa Hsu 283691Shsul@eecs.umich.edu 293691Shsul@eecs.umich.eduimport m5 303691Shsul@eecs.umich.edufrom m5.objects import * 3111682Sandreas.hansson@arm.comm5.util.addToPath('../configs/') 3213916Sodanrc@yahoo.com.brfrom common import Benchmarks, FSConfig, SysPaths 333691Shsul@eecs.umich.edu 3413950Sodanrc@yahoo.com.brtest_sys = FSConfig.makeLinuxAlphaSystem('atomic', 3513950Sodanrc@yahoo.com.br Benchmarks.SysConfig('netperf-stream-client.rcS')) 3613916Sodanrc@yahoo.com.brtest_sys.kernel = SysPaths.binary('vmlinux') 379793Sakash.bagdia@arm.com 389827Sakash.bagdia@arm.com# Dummy voltage domain for all test_sys clock domains 399827Sakash.bagdia@arm.comtest_sys.voltage_domain = VoltageDomain() 409827Sakash.bagdia@arm.com 419793Sakash.bagdia@arm.com# Create the system clock domain 429827Sakash.bagdia@arm.comtest_sys.clk_domain = SrcClockDomain(clock = '1GHz', 439827Sakash.bagdia@arm.com voltage_domain = test_sys.voltage_domain) 449793Sakash.bagdia@arm.com 453691Shsul@eecs.umich.edutest_sys.cpu = AtomicSimpleCPU(cpu_id=0) 468876Sandreas.hansson@arm.com# create the interrupt controller 478876Sandreas.hansson@arm.comtest_sys.cpu.createInterruptController() 487876Sgblack@eecs.umich.edutest_sys.cpu.connectAllPorts(test_sys.membus) 499793Sakash.bagdia@arm.com 509793Sakash.bagdia@arm.com# Create a seperate clock domain for components that should run at 519793Sakash.bagdia@arm.com# CPUs frequency 529827Sakash.bagdia@arm.comtest_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 539827Sakash.bagdia@arm.com voltage_domain = 549827Sakash.bagdia@arm.com test_sys.voltage_domain) 559793Sakash.bagdia@arm.com 569793Sakash.bagdia@arm.com# Create a separate clock domain for Ethernet 579827Sakash.bagdia@arm.comtest_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', 589827Sakash.bagdia@arm.com voltage_domain = 599827Sakash.bagdia@arm.com test_sys.voltage_domain) 609793Sakash.bagdia@arm.com 618713Sandreas.hansson@arm.com# In contrast to the other (one-system) Tsunami configurations we do 628713Sandreas.hansson@arm.com# not have an IO cache but instead rely on an IO bridge for accesses 638713Sandreas.hansson@arm.com# from masters on the IO bus to the memory bus 649408Sandreas.hansson@arm.comtest_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 658839Sandreas.hansson@arm.comtest_sys.iobridge.slave = test_sys.iobus.master 668839Sandreas.hansson@arm.comtest_sys.iobridge.master = test_sys.membus.slave 673691Shsul@eecs.umich.edu 689826Sandreas.hansson@arm.comtest_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0]) 699826Sandreas.hansson@arm.comtest_sys.physmem.port = test_sys.membus.master 709826Sandreas.hansson@arm.com 7113950Sodanrc@yahoo.com.brdrive_sys = FSConfig.makeLinuxAlphaSystem('atomic', 7213950Sodanrc@yahoo.com.br Benchmarks.SysConfig('netperf-server.rcS')) 7313916Sodanrc@yahoo.com.brdrive_sys.kernel = SysPaths.binary('vmlinux') 749827Sakash.bagdia@arm.com# Dummy voltage domain for all drive_sys clock domains 759827Sakash.bagdia@arm.comdrive_sys.voltage_domain = VoltageDomain() 769793Sakash.bagdia@arm.com# Create the system clock domain 779827Sakash.bagdia@arm.comdrive_sys.clk_domain = SrcClockDomain(clock = '1GHz', 789827Sakash.bagdia@arm.com voltage_domain = 799827Sakash.bagdia@arm.com drive_sys.voltage_domain) 803691Shsul@eecs.umich.edudrive_sys.cpu = AtomicSimpleCPU(cpu_id=0) 818876Sandreas.hansson@arm.com# create the interrupt controller 828876Sandreas.hansson@arm.comdrive_sys.cpu.createInterruptController() 837876Sgblack@eecs.umich.edudrive_sys.cpu.connectAllPorts(drive_sys.membus) 849793Sakash.bagdia@arm.com 859793Sakash.bagdia@arm.com# Create a seperate clock domain for components that should run at 869793Sakash.bagdia@arm.com# CPUs frequency 879827Sakash.bagdia@arm.comdrive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz', 889827Sakash.bagdia@arm.com voltage_domain = 899827Sakash.bagdia@arm.com drive_sys.voltage_domain) 909793Sakash.bagdia@arm.com 919793Sakash.bagdia@arm.com# Create a separate clock domain for Ethernet 929827Sakash.bagdia@arm.comdrive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', 939827Sakash.bagdia@arm.com voltage_domain = 949827Sakash.bagdia@arm.com drive_sys.voltage_domain) 959793Sakash.bagdia@arm.com 969408Sandreas.hansson@arm.comdrive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) 978839Sandreas.hansson@arm.comdrive_sys.iobridge.slave = drive_sys.iobus.master 988839Sandreas.hansson@arm.comdrive_sys.iobridge.master = drive_sys.membus.slave 993691Shsul@eecs.umich.edu 1009826Sandreas.hansson@arm.comdrive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0]) 1019826Sandreas.hansson@arm.comdrive_sys.physmem.port = drive_sys.membus.master 1029826Sandreas.hansson@arm.com 10313950Sodanrc@yahoo.com.brroot = FSConfig.makeDualRoot(True, test_sys, drive_sys, "ethertrace") 1043691Shsul@eecs.umich.edu 1053691Shsul@eecs.umich.edumaxtick = 199999999 106