110249Sstephan.diestelhorst@arm.com# Copyright (c) 2013-2014 ARM Limited 210249Sstephan.diestelhorst@arm.com# All rights reserved. 310249Sstephan.diestelhorst@arm.com# 410249Sstephan.diestelhorst@arm.com# The license below extends only to copyright in the software and shall 510249Sstephan.diestelhorst@arm.com# not be construed as granting a license to any other intellectual 610249Sstephan.diestelhorst@arm.com# property including but not limited to intellectual property relating 710249Sstephan.diestelhorst@arm.com# to a hardware implementation of the functionality of the software 810249Sstephan.diestelhorst@arm.com# licensed hereunder. You may use the software subject to the license 910249Sstephan.diestelhorst@arm.com# terms below provided that you ensure that this notice is replicated 1010249Sstephan.diestelhorst@arm.com# unmodified and in its entirety in all distributions of the software, 1110249Sstephan.diestelhorst@arm.com# modified or unmodified, in source code or in binary form. 1210249Sstephan.diestelhorst@arm.com# 1310249Sstephan.diestelhorst@arm.com# Redistribution and use in source and binary forms, with or without 1410249Sstephan.diestelhorst@arm.com# modification, are permitted provided that the following conditions are 1510249Sstephan.diestelhorst@arm.com# met: redistributions of source code must retain the above copyright 1610249Sstephan.diestelhorst@arm.com# notice, this list of conditions and the following disclaimer; 1710249Sstephan.diestelhorst@arm.com# redistributions in binary form must reproduce the above copyright 1810249Sstephan.diestelhorst@arm.com# notice, this list of conditions and the following disclaimer in the 1910249Sstephan.diestelhorst@arm.com# documentation and/or other materials provided with the distribution; 2010249Sstephan.diestelhorst@arm.com# neither the name of the copyright holders nor the names of its 2110249Sstephan.diestelhorst@arm.com# contributors may be used to endorse or promote products derived from 2210249Sstephan.diestelhorst@arm.com# this software without specific prior written permission. 2310249Sstephan.diestelhorst@arm.com# 2410249Sstephan.diestelhorst@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510249Sstephan.diestelhorst@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610249Sstephan.diestelhorst@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710249Sstephan.diestelhorst@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810249Sstephan.diestelhorst@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910249Sstephan.diestelhorst@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010249Sstephan.diestelhorst@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110249Sstephan.diestelhorst@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210249Sstephan.diestelhorst@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310249Sstephan.diestelhorst@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410249Sstephan.diestelhorst@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510249Sstephan.diestelhorst@arm.com# 3610249Sstephan.diestelhorst@arm.com# Authors: Vasileios Spiliopoulos 3710249Sstephan.diestelhorst@arm.com# Akash Bagdia 3810249Sstephan.diestelhorst@arm.com 3910249Sstephan.diestelhorst@arm.comfrom m5.params import * 4010249Sstephan.diestelhorst@arm.comfrom m5.SimObject import SimObject 4110249Sstephan.diestelhorst@arm.comfrom m5.proxy import * 4210249Sstephan.diestelhorst@arm.com 4310249Sstephan.diestelhorst@arm.com# The handler in its current form is design to be centeralized, one per system 4410249Sstephan.diestelhorst@arm.com# and manages all the source clock domains (SrcClockDomain) it is configured to 4510249Sstephan.diestelhorst@arm.com# handle. The specific voltage and frequency points are configured per clock 4610249Sstephan.diestelhorst@arm.com# and voltage domain. 4710249Sstephan.diestelhorst@arm.comclass DVFSHandler(SimObject): 4810249Sstephan.diestelhorst@arm.com type = 'DVFSHandler' 4910249Sstephan.diestelhorst@arm.com cxx_header = "sim/dvfs_handler.hh" 5010249Sstephan.diestelhorst@arm.com 5110249Sstephan.diestelhorst@arm.com # List of controllable clock domains which in turn reference the appropriate 5210249Sstephan.diestelhorst@arm.com # voltage domains 5310249Sstephan.diestelhorst@arm.com domains = VectorParam.SrcClockDomain([], "list of domains") 5410249Sstephan.diestelhorst@arm.com 5510249Sstephan.diestelhorst@arm.com # System domain (its clock and voltage) is not controllable 5610249Sstephan.diestelhorst@arm.com sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain, 5710249Sstephan.diestelhorst@arm.com "Clk domain in which the handler is instantiated") 5810249Sstephan.diestelhorst@arm.com 5910249Sstephan.diestelhorst@arm.com enable = Param.Bool(False, "Enable/Disable the handler") 6010249Sstephan.diestelhorst@arm.com 6110249Sstephan.diestelhorst@arm.com # The transition latency depends on how much time the PLLs and voltage 6210249Sstephan.diestelhorst@arm.com # regualators takes to migrate from current levels to the new level, is 6310249Sstephan.diestelhorst@arm.com # usally variable and hardware implementation dependent. In order to 6410249Sstephan.diestelhorst@arm.com # accomodate this effect with ease, we provide a fixed transition latency 6510249Sstephan.diestelhorst@arm.com # associated with all migrations. Configure this to maximum latency that 6610249Sstephan.diestelhorst@arm.com # the hardware will take to migratate between any two perforamnce levels. 6710249Sstephan.diestelhorst@arm.com transition_latency = Param.Latency('100us', 6810249Sstephan.diestelhorst@arm.com "fixed latency for perf level migration") 69