16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26166Ssteve.reinhardt@amd.com# All rights reserved. 36166Ssteve.reinhardt@amd.com# 46166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 56166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 66166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 76166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 86166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 96166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 106166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 116166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 126166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 136166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 146166Ssteve.reinhardt@amd.com# 156166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266166Ssteve.reinhardt@amd.com# 276166Ssteve.reinhardt@amd.com# Authors: Steve Reinhardt 286166Ssteve.reinhardt@amd.com 296166Ssteve.reinhardt@amd.comimport m5 306166Ssteve.reinhardt@amd.comfrom m5.objects import * 316928SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 326928SBrad.Beckmann@amd.comfrom m5.util import addToPath 336928SBrad.Beckmann@amd.comimport os, optparse, sys 346166Ssteve.reinhardt@amd.com 3511670Sandreas.hansson@arm.comm5.util.addToPath('../configs/') 366928SBrad.Beckmann@amd.com 3711670Sandreas.hansson@arm.comfrom ruby import Ruby 3811682Sandreas.hansson@arm.comfrom common import Options 396928SBrad.Beckmann@amd.com 406928SBrad.Beckmann@amd.comparser = optparse.OptionParser() 418920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 426928SBrad.Beckmann@amd.com 437570SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 447570SBrad.Beckmann@amd.comRuby.define_options(parser) 456928SBrad.Beckmann@amd.com 466928SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 476928SBrad.Beckmann@amd.com 487570SBrad.Beckmann@amd.com# 497570SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 507570SBrad.Beckmann@amd.com# races between requests and writebacks. 517570SBrad.Beckmann@amd.com# 527570SBrad.Beckmann@amd.comoptions.l1d_size="256B" 537570SBrad.Beckmann@amd.comoptions.l1i_size="256B" 547570SBrad.Beckmann@amd.comoptions.l2_size="512B" 557570SBrad.Beckmann@amd.comoptions.l3_size="1kB" 567570SBrad.Beckmann@amd.comoptions.l1d_assoc=2 577570SBrad.Beckmann@amd.comoptions.l1i_assoc=2 587570SBrad.Beckmann@amd.comoptions.l2_assoc=2 597570SBrad.Beckmann@amd.comoptions.l3_assoc=2 607570SBrad.Beckmann@amd.com 616928SBrad.Beckmann@amd.com# this is a uniprocessor only test 626928SBrad.Beckmann@amd.comoptions.num_cpus = 1 6310524Snilay@cs.wisc.educpu = TimingSimpleCPU(cpu_id=0) 6410524Snilay@cs.wisc.edusystem = System(cpu = cpu) 656289Snate@binkert.org 669827Sakash.bagdia@arm.com# Dummy voltage domain for all our clock domains 679827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 689827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 699827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 709793Sakash.bagdia@arm.com 719793Sakash.bagdia@arm.com# Create a seperate clock domain for components that should run at 729793Sakash.bagdia@arm.com# CPUs frequency 739827Sakash.bagdia@arm.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 749827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 756928SBrad.Beckmann@amd.com 769826Sandreas.hansson@arm.comsystem.mem_ranges = AddrRange('256MB') 7710519Snilay@cs.wisc.eduRuby.create_system(options, False, system) 786928SBrad.Beckmann@amd.com 799793Sakash.bagdia@arm.com# Create a separate clock for Ruby 809827Sakash.bagdia@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 819827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 829793Sakash.bagdia@arm.com 8310120Snilay@cs.wisc.eduassert(len(system.ruby._cpu_ports) == 1) 846928SBrad.Beckmann@amd.com 858876Sandreas.hansson@arm.com# create the interrupt controller 868876Sandreas.hansson@arm.comcpu.createInterruptController() 878876Sandreas.hansson@arm.com 886928SBrad.Beckmann@amd.com# 896928SBrad.Beckmann@amd.com# Tie the cpu cache ports to the ruby cpu ports and 906928SBrad.Beckmann@amd.com# physmem, respectively 916928SBrad.Beckmann@amd.com# 9210120Snilay@cs.wisc.educpu.connectAllPorts(system.ruby._cpu_ports[0]) 936928SBrad.Beckmann@amd.com 946928SBrad.Beckmann@amd.com# ----------------------- 956928SBrad.Beckmann@amd.com# run simulation 966928SBrad.Beckmann@amd.com# ----------------------- 976166Ssteve.reinhardt@amd.com 988801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 996928SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing' 100