14019SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 23187SN/A# All rights reserved. 33187SN/A# 43187SN/A# Redistribution and use in source and binary forms, with or without 53187SN/A# modification, are permitted provided that the following conditions are 63187SN/A# met: redistributions of source code must retain the above copyright 73187SN/A# notice, this list of conditions and the following disclaimer; 83187SN/A# redistributions in binary form must reproduce the above copyright 93187SN/A# notice, this list of conditions and the following disclaimer in the 103187SN/A# documentation and/or other materials provided with the distribution; 113187SN/A# neither the name of the copyright holders nor the names of its 123187SN/A# contributors may be used to endorse or promote products derived from 133187SN/A# this software without specific prior written permission. 143187SN/A# 153187SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 163187SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 173187SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 183187SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 193187SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 203187SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 213187SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 223187SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 233187SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 243187SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 253187SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 263187SN/A# 273187SN/A# Authors: Ron Dreslinski 283187SN/A 293187SN/Aimport m5 303187SN/Afrom m5.objects import * 3111682Sandreas.hansson@arm.comm5.util.addToPath('../configs/') 3211682Sandreas.hansson@arm.comfrom common.Caches import * 333187SN/A 343196SN/A#MAX CORES IS 8 with the fals sharing method 353196SN/Anb_cores = 8 3613718Sandreas.sandberg@arm.comcpus = [ MemTest() for i in range(nb_cores) ] 373187SN/A 383187SN/A# system simulated 3910688Sandreas.hansson@arm.comsystem = System(cpu = cpus, 408931SN/A physmem = SimpleMemory(), 4110720Sandreas.hansson@arm.com membus = SystemXBar(width=16, snoop_filter = SnoopFilter())) 429827SN/A# Dummy voltage domain for all our clock domains 439827SN/Asystem.voltage_domain = VoltageDomain() 449827SN/Asystem.clk_domain = SrcClockDomain(clock = '1GHz', 459827SN/A voltage_domain = system.voltage_domain) 463187SN/A 479793SN/A# Create a seperate clock domain for components that should run at 489793SN/A# CPUs frequency 499827SN/Asystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 509827SN/A voltage_domain = system.voltage_domain) 519793SN/A 5210720Sandreas.hansson@arm.comsystem.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain, 5310720Sandreas.hansson@arm.com snoop_filter = SnoopFilter()) 549793SN/Asystem.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 558839SN/Asystem.l2c.cpu_side = system.toL2Bus.master 563187SN/A 573187SN/A# connect l2c to membus 588839SN/Asystem.l2c.mem_side = system.membus.slave 593187SN/A 603187SN/A# add L1 caches 613187SN/Afor cpu in cpus: 629793SN/A # All cpus are associated with cpu_clk_domain 639793SN/A cpu.clk_domain = system.cpu_clk_domain 649321SN/A cpu.l1c = L1Cache(size = '32kB', assoc = 4) 6510688Sandreas.hansson@arm.com cpu.l1c.cpu_side = cpu.port 668839SN/A cpu.l1c.mem_side = system.toL2Bus.slave 673187SN/A 688839SN/Asystem.system_port = system.membus.slave 698706SN/A 703187SN/A# connect memory to membus 718839SN/Asystem.physmem.port = system.membus.master 723187SN/A 733187SN/A 743187SN/A# ----------------------- 753187SN/A# run simulation 763187SN/A# ----------------------- 773187SN/A 788801SN/Aroot = Root( full_system = False, system = system ) 793187SN/Aroot.system.mem_mode = 'timing' 80