19242SN/A# Copyright (c) 2012 ARM Limited
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359242SN/A#
369242SN/A# Authors: Andreas Hansson
379242SN/A
389242SN/Aimport m5
399242SN/Afrom m5.objects import *
409242SN/A
419402SN/A# both traffic generator and communication monitor are only available
429402SN/A# if we have protobuf support, so potentially skip this test
439402SN/Arequire_sim_object("TrafficGen")
449402SN/Arequire_sim_object("CommMonitor")
459402SN/A
469242SN/A# even if this is only a traffic generator, call it cpu to make sure
479242SN/A# the scripts are happy
4811516Sandreas.sandberg@arm.comcpu = TrafficGen(
4911516Sandreas.sandberg@arm.com    config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
509242SN/A
519242SN/A# system simulated
5211837Swendy.elsasser@arm.comsystem = System(cpu = cpu, physmem = DDR3_1600_8x8(),
5310720Sandreas.hansson@arm.com                membus = IOXBar(width = 16),
549827SN/A                clk_domain = SrcClockDomain(clock = '1GHz',
559827SN/A                                            voltage_domain =
569827SN/A                                            VoltageDomain()))
579242SN/A
589242SN/A# add a communication monitor
599242SN/Asystem.monitor = CommMonitor()
609242SN/A
619242SN/A# connect the traffic generator to the bus via a communication monitor
629242SN/Asystem.cpu.port = system.monitor.slave
639242SN/Asystem.monitor.master = system.membus.slave
649242SN/A
659242SN/A# connect the system port even if it is not used in this example
669242SN/Asystem.system_port = system.membus.slave
679242SN/A
689242SN/A# connect memory to the membus
699242SN/Asystem.physmem.port = system.membus.master
709242SN/A
719242SN/A# -----------------------
729242SN/A# run simulation
739242SN/A# -----------------------
749242SN/A
759242SN/Aroot = Root(full_system = False, system = system)
769242SN/Aroot.system.mem_mode = 'timing'
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