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35#
36# Authors: Andreas Hansson
37
38import m5
39from m5.objects import *
40
41# both traffic generator and communication monitor are only available
42# if we have protobuf support, so potentially skip this test
43require_sim_object("TrafficGen")
44require_sim_object("CommMonitor")
45
46# even if this is only a traffic generator, call it cpu to make sure
47# the scripts are happy
48cpu = TrafficGen(
49    config_file=srcpath("tests/quick/se/70.tgen/tgen-dram-ctrl.cfg"))
50
51# system simulated
52system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
53                membus = IOXBar(width = 16),
54                clk_domain = SrcClockDomain(clock = '1GHz',
55                                            voltage_domain =
56                                            VoltageDomain()))
57
58# add a communication monitor
59system.monitor = CommMonitor()
60
61# connect the traffic generator to the bus via a communication monitor
62system.cpu.port = system.monitor.slave
63system.monitor.master = system.membus.slave
64
65# connect the system port even if it is not used in this example
66system.system_port = system.membus.slave
67
68# connect memory to the membus
69system.physmem.port = system.membus.master
70
71# -----------------------
72# run simulation
73# -----------------------
74
75root = Root(full_system = False, system = system)
76root.system.mem_mode = 'timing'
77