1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/')
32from common.Caches import *
33
34#MAX CORES IS 8 with the fals sharing method
35nb_cores = 8
36cpus = [ MemTest() for i in range(nb_cores) ]
37
38# system simulated
39system = System(cpu = cpus,
40                physmem = SimpleMemory(),
41                membus = SystemXBar())
42# Dummy voltage domain for all our clock domains
43system.voltage_domain = VoltageDomain()
44system.clk_domain = SrcClockDomain(clock = '1GHz',
45                                   voltage_domain = system.voltage_domain)
46
47# Create a seperate clock domain for components that should run at
48# CPUs frequency
49system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
50                                       voltage_domain = system.voltage_domain)
51
52system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain)
53system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
54system.l2c.cpu_side = system.toL2Bus.master
55
56# connect l2c to membus
57system.l2c.mem_side = system.membus.slave
58
59# add L1 caches
60for cpu in cpus:
61    # All cpus are associated with cpu_clk_domain
62    cpu.clk_domain = system.cpu_clk_domain
63    cpu.l1c = L1Cache(size = '32kB', assoc = 4)
64    cpu.l1c.cpu_side = cpu.port
65    cpu.l1c.mem_side = system.toL2Bus.slave
66
67system.system_port = system.membus.slave
68
69# connect memory to membus
70system.physmem.port = system.membus.master
71
72
73# -----------------------
74# run simulation
75# -----------------------
76
77root = Root( full_system = False, system = system )
78root.system.mem_mode = 'timing'
79
80