1# Copyright (c) 2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ali Saidi
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/')
32from common import FSConfig
33
34try:
35    system = FSConfig.makeSparcSystem('atomic')
36except IOError as e:
37    skip_test(reason=str(e))
38
39system.voltage_domain = VoltageDomain()
40system.clk_domain = SrcClockDomain(clock = '1GHz',
41                                   voltage_domain = system.voltage_domain)
42system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
43                                       voltage_domain = system.voltage_domain)
44cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
45system.cpu = cpu
46# create the interrupt controller
47cpu.createInterruptController()
48cpu.connectAllPorts(system.membus)
49
50# create the memory controllers and connect them, stick with
51# the physmem name to avoid bumping all the reference stats
52system.physmem = [SimpleMemory(range = r)
53                  for r in system.mem_ranges]
54for i in range(len(system.physmem)):
55    system.physmem[i].port = system.membus.master
56
57root = Root(full_system=True, system=system)
58
59m5.ticks.setGlobalFrequency('2GHz')
60