1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31from m5.defines import buildEnv
32from m5.util import addToPath
33import os, optparse, sys
34
35m5.util.addToPath('../configs/')
36
37from common import Options
38from ruby import Ruby
39
40parser = optparse.OptionParser()
41Options.addCommonOptions(parser)
42
43# Add the ruby specific and protocol specific options
44Ruby.define_options(parser)
45
46(options, args) = parser.parse_args()
47
48#
49# Set the default cache size and associativity to be very small to encourage
50# races between requests and writebacks.
51#
52options.l1d_size="256B"
53options.l1i_size="256B"
54options.l2_size="512B"
55options.l3_size="1kB"
56options.l1d_assoc=2
57options.l1i_assoc=2
58options.l2_assoc=2
59options.l3_assoc=2
60
61nb_cores = 4
62cpus = [ TimingSimpleCPU(cpu_id=i) for i in range(nb_cores) ]
63
64# overwrite the num_cpus to equal nb_cores
65options.num_cpus = nb_cores
66
67# system simulated
68system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
69
70# Create a seperate clock domain for components that should run at
71# CPUs frequency
72system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
73
74Ruby.create_system(options, False, system)
75
76# Create a separate clock domain for Ruby
77system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
78
79assert(options.num_cpus == len(system.ruby._cpu_ports))
80
81for (i, cpu) in enumerate(system.cpu):
82    # create the interrupt controller
83    cpu.createInterruptController()
84
85    #
86    # Tie the cpu ports to the ruby cpu ports
87    #
88    cpu.connectAllPorts(system.ruby._cpu_ports[i])
89
90# -----------------------
91# run simulation
92# -----------------------
93
94root = Root( full_system=False, system = system )
95root.system.mem_mode = 'timing'
96