112047Schristian.menard@tu-dresden.de# Copyright (c) 2016, University of Kaiserslautern 212047Schristian.menard@tu-dresden.de# All rights reserved. 312047Schristian.menard@tu-dresden.de# 412047Schristian.menard@tu-dresden.de# Redistribution and use in source and binary forms, with or without 512047Schristian.menard@tu-dresden.de# modification, are permitted provided that the following conditions are 612047Schristian.menard@tu-dresden.de# met: 712047Schristian.menard@tu-dresden.de# 812047Schristian.menard@tu-dresden.de# 1. Redistributions of source code must retain the above copyright notice, 912047Schristian.menard@tu-dresden.de# this list of conditions and the following disclaimer. 1012047Schristian.menard@tu-dresden.de# 1112047Schristian.menard@tu-dresden.de# 2. Redistributions in binary form must reproduce the above copyright 1212047Schristian.menard@tu-dresden.de# notice, this list of conditions and the following disclaimer in the 1312047Schristian.menard@tu-dresden.de# documentation and/or other materials provided with the distribution. 1412047Schristian.menard@tu-dresden.de# 1512047Schristian.menard@tu-dresden.de# 3. Neither the name of the copyright holder nor the names of its 1612047Schristian.menard@tu-dresden.de# contributors may be used to endorse or promote products derived from 1712047Schristian.menard@tu-dresden.de# this software without specific prior written permission. 1812047Schristian.menard@tu-dresden.de# 1912047Schristian.menard@tu-dresden.de# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2012047Schristian.menard@tu-dresden.de# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2112047Schristian.menard@tu-dresden.de# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2212047Schristian.menard@tu-dresden.de# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER 2312047Schristian.menard@tu-dresden.de# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 2412047Schristian.menard@tu-dresden.de# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2512047Schristian.menard@tu-dresden.de# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 2612047Schristian.menard@tu-dresden.de# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 2712047Schristian.menard@tu-dresden.de# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 2812047Schristian.menard@tu-dresden.de# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 2912047Schristian.menard@tu-dresden.de# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3012047Schristian.menard@tu-dresden.de# 3112047Schristian.menard@tu-dresden.de# Authors: Matthias Jung 3212047Schristian.menard@tu-dresden.de 3312047Schristian.menard@tu-dresden.deimport m5 3412047Schristian.menard@tu-dresden.deimport optparse 3512047Schristian.menard@tu-dresden.de 3612047Schristian.menard@tu-dresden.defrom m5.objects import * 3712047Schristian.menard@tu-dresden.defrom m5.util import addToPath, fatal 3812047Schristian.menard@tu-dresden.de 3912047Schristian.menard@tu-dresden.deaddToPath('../../../configs/common/') 4012047Schristian.menard@tu-dresden.de 4112047Schristian.menard@tu-dresden.defrom Caches import * 4212047Schristian.menard@tu-dresden.de 4312047Schristian.menard@tu-dresden.de# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU) 4412047Schristian.menard@tu-dresden.de# and an external TLM port for SystemC co-simulation. 4512047Schristian.menard@tu-dresden.de# 4612047Schristian.menard@tu-dresden.de# We assume a DRAM size of 512MB and L1 cache sizes of 32KB. 4712047Schristian.menard@tu-dresden.de# 4812047Schristian.menard@tu-dresden.de# Base System Architecture: 4912047Schristian.menard@tu-dresden.de# 5012047Schristian.menard@tu-dresden.de# +-----------+ ^ 5112047Schristian.menard@tu-dresden.de# +-------------+ | eTraceCPU | | 5212047Schristian.menard@tu-dresden.de# | System Port | +-----+-----+ | 5312047Schristian.menard@tu-dresden.de# +------+------+ | $D1 | $I1 | | 5412047Schristian.menard@tu-dresden.de# | +--+--+--+--+ | 5512047Schristian.menard@tu-dresden.de# | | | | gem5 World 5612047Schristian.menard@tu-dresden.de# | | | | (see this file) 5712047Schristian.menard@tu-dresden.de# | | | | 5812047Schristian.menard@tu-dresden.de# +------v------------v-----v--+ | 5912047Schristian.menard@tu-dresden.de# | Membus | v 6012047Schristian.menard@tu-dresden.de# +----------------+-----------+ External Port (see sc_port.*) 6112047Schristian.menard@tu-dresden.de# | ^ 6212047Schristian.menard@tu-dresden.de# +---v---+ | TLM World 6312047Schristian.menard@tu-dresden.de# | TLM | | (see sc_target.*) 6412047Schristian.menard@tu-dresden.de# +-------+ v 6512047Schristian.menard@tu-dresden.de# 6612047Schristian.menard@tu-dresden.de# 6712047Schristian.menard@tu-dresden.de# Create a system with a Crossbar and an Elastic Trace Player as CPU: 6812047Schristian.menard@tu-dresden.de 6912047Schristian.menard@tu-dresden.de# Setup System: 7012047Schristian.menard@tu-dresden.desystem = System(cpu=TraceCPU(cpu_id=0), 7112047Schristian.menard@tu-dresden.de mem_mode='timing', 7212047Schristian.menard@tu-dresden.de mem_ranges = [AddrRange('512MB')], 7312047Schristian.menard@tu-dresden.de cache_line_size = 64) 7412047Schristian.menard@tu-dresden.de 7512047Schristian.menard@tu-dresden.de# Create a top-level voltage domain: 7612047Schristian.menard@tu-dresden.desystem.voltage_domain = VoltageDomain() 7712047Schristian.menard@tu-dresden.de 7812047Schristian.menard@tu-dresden.de# Create a source clock for the system. This is used as the clock period for 7912047Schristian.menard@tu-dresden.de# xbar and memory: 8012047Schristian.menard@tu-dresden.desystem.clk_domain = SrcClockDomain(clock = '1GHz', 8112047Schristian.menard@tu-dresden.de voltage_domain = system.voltage_domain) 8212047Schristian.menard@tu-dresden.de 8312047Schristian.menard@tu-dresden.de# Create a CPU voltage domain: 8412047Schristian.menard@tu-dresden.desystem.cpu_voltage_domain = VoltageDomain() 8512047Schristian.menard@tu-dresden.de 8612047Schristian.menard@tu-dresden.de# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock 8712047Schristian.menard@tu-dresden.de# is actually used only by the caches connected to the CPU: 8812047Schristian.menard@tu-dresden.desystem.cpu_clk_domain = SrcClockDomain(clock = '1GHz', 8912047Schristian.menard@tu-dresden.de voltage_domain = system.cpu_voltage_domain) 9012047Schristian.menard@tu-dresden.de 9112047Schristian.menard@tu-dresden.de# Setup CPU and its L1 caches: 9212047Schristian.menard@tu-dresden.desystem.cpu.createInterruptController() 9312047Schristian.menard@tu-dresden.desystem.cpu.icache = L1_ICache(size="32kB") 9412047Schristian.menard@tu-dresden.desystem.cpu.dcache = L1_DCache(size="32kB") 9512047Schristian.menard@tu-dresden.desystem.cpu.icache.cpu_side = system.cpu.icache_port 9612047Schristian.menard@tu-dresden.desystem.cpu.dcache.cpu_side = system.cpu.dcache_port 9712047Schristian.menard@tu-dresden.de 9812047Schristian.menard@tu-dresden.de# Assign input trace files to the eTraceCPU: 9912047Schristian.menard@tu-dresden.desystem.cpu.instTraceFile="system.cpu.traceListener.inst.gz" 10012047Schristian.menard@tu-dresden.desystem.cpu.dataTraceFile="system.cpu.traceListener.data.gz" 10112047Schristian.menard@tu-dresden.de 10212047Schristian.menard@tu-dresden.de# Setting up L1 BUS: 10312047Schristian.menard@tu-dresden.desystem.membus = IOXBar(width = 16) 10412047Schristian.menard@tu-dresden.desystem.physmem = SimpleMemory() # This must be instantiated, even if not needed 10512047Schristian.menard@tu-dresden.de 10612047Schristian.menard@tu-dresden.de# Create a external TLM port: 10712047Schristian.menard@tu-dresden.desystem.tlm = ExternalSlave() 10812047Schristian.menard@tu-dresden.desystem.tlm.addr_ranges = [AddrRange('512MB')] 10912047Schristian.menard@tu-dresden.desystem.tlm.port_type = "tlm_slave" 11012047Schristian.menard@tu-dresden.desystem.tlm.port_data = "transactor" 11112047Schristian.menard@tu-dresden.de 11212047Schristian.menard@tu-dresden.de# Connect everything: 11312047Schristian.menard@tu-dresden.desystem.membus = SystemXBar() 11412047Schristian.menard@tu-dresden.desystem.system_port = system.membus.slave 11512047Schristian.menard@tu-dresden.desystem.cpu.icache.mem_side = system.membus.slave 11612047Schristian.menard@tu-dresden.desystem.cpu.dcache.mem_side = system.membus.slave 11712047Schristian.menard@tu-dresden.desystem.membus.master = system.tlm.port 11812047Schristian.menard@tu-dresden.de 11912047Schristian.menard@tu-dresden.de# Start the simulation: 12012047Schristian.menard@tu-dresden.deroot = Root(full_system = False, system = system) 12112047Schristian.menard@tu-dresden.deroot.system.mem_mode = 'timing' 12212047Schristian.menard@tu-dresden.dem5.instantiate() 12312047Schristian.menard@tu-dresden.dem5.simulate() #Simulation time specified later on commandline 124