1# Copyright (c) 2016, University of Kaiserslautern
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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9#    this list of conditions and the following disclaimer.
10#
11# 2. Redistributions in binary form must reproduce the above copyright
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17#    this software without specific prior written permission.
18#
19# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
23# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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28# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30#
31# Authors: Matthias Jung
32
33import m5
34import optparse
35
36from m5.objects import *
37from m5.util import addToPath, fatal
38
39addToPath('../../../configs/common/')
40
41from Caches import *
42
43# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
44# and an external TLM port for SystemC co-simulation.
45#
46# We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
47#
48# Base System Architecture:
49#
50#                  +-----------+       ^
51# +-------------+  | eTraceCPU |       |
52# | System Port |  +-----+-----+       |
53# +------+------+  | $D1 | $I1 |       |
54#        |         +--+--+--+--+       |
55#        |            |     |          | gem5 World
56#        |            |     |          | (see this file)
57#        |            |     |          |
58# +------v------------v-----v--+       |
59# |           Membus           |       v
60# +----------------+-----------+       External Port (see sc_port.*)
61#                  |                   ^
62#              +---v---+               | TLM World
63#              |  TLM  |               | (see sc_target.*)
64#              +-------+               v
65#
66#
67# Create a system with a Crossbar and an Elastic Trace Player as CPU:
68
69# Setup System:
70system = System(cpu=TraceCPU(cpu_id=0),
71                mem_mode='timing',
72                mem_ranges = [AddrRange('512MB')],
73                cache_line_size = 64)
74
75# Create a top-level voltage domain:
76system.voltage_domain = VoltageDomain()
77
78# Create a source clock for the system. This is used as the clock period for
79# xbar and memory:
80system.clk_domain = SrcClockDomain(clock =  '1GHz',
81        voltage_domain = system.voltage_domain)
82
83# Create a CPU voltage domain:
84system.cpu_voltage_domain = VoltageDomain()
85
86# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
87# is actually used only by the caches connected to the CPU:
88system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',
89        voltage_domain = system.cpu_voltage_domain)
90
91# Setup CPU and its L1 caches:
92system.cpu.createInterruptController()
93system.cpu.icache = L1_ICache(size="32kB")
94system.cpu.dcache = L1_DCache(size="32kB")
95system.cpu.icache.cpu_side = system.cpu.icache_port
96system.cpu.dcache.cpu_side = system.cpu.dcache_port
97
98# Assign input trace files to the eTraceCPU:
99system.cpu.instTraceFile="system.cpu.traceListener.inst.gz"
100system.cpu.dataTraceFile="system.cpu.traceListener.data.gz"
101
102# Setting up L1 BUS:
103system.membus = IOXBar(width = 16)
104system.physmem = SimpleMemory() # This must be instantiated, even if not needed
105
106# Create a external TLM port:
107system.tlm = ExternalSlave()
108system.tlm.addr_ranges = [AddrRange('512MB')]
109system.tlm.port_type = "tlm_slave"
110system.tlm.port_data = "transactor"
111
112# Connect everything:
113system.membus = SystemXBar()
114system.system_port = system.membus.slave
115system.cpu.icache.mem_side = system.membus.slave
116system.cpu.dcache.mem_side = system.membus.slave
117system.membus.master = system.tlm.port
118
119# Start the simulation:
120root = Root(full_system = False, system = system)
121root.system.mem_mode = 'timing'
122m5.instantiate()
123m5.simulate() #Simulation time specified later on commandline
124