113677Sjason@lowepower.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 213677Sjason@lowepower.com# All rights reserved. 313677Sjason@lowepower.com# 413677Sjason@lowepower.com# Redistribution and use in source and binary forms, with or without 513677Sjason@lowepower.com# modification, are permitted provided that the following conditions are 613677Sjason@lowepower.com# met: redistributions of source code must retain the above copyright 713677Sjason@lowepower.com# notice, this list of conditions and the following disclaimer; 813677Sjason@lowepower.com# redistributions in binary form must reproduce the above copyright 913677Sjason@lowepower.com# notice, this list of conditions and the following disclaimer in the 1013677Sjason@lowepower.com# documentation and/or other materials provided with the distribution; 1113677Sjason@lowepower.com# neither the name of the copyright holders nor the names of its 1213677Sjason@lowepower.com# contributors may be used to endorse or promote products derived from 1313677Sjason@lowepower.com# this software without specific prior written permission. 1413677Sjason@lowepower.com# 1513677Sjason@lowepower.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1613677Sjason@lowepower.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1713677Sjason@lowepower.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1813677Sjason@lowepower.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1913677Sjason@lowepower.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2013677Sjason@lowepower.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2113677Sjason@lowepower.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2213677Sjason@lowepower.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2313677Sjason@lowepower.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2413677Sjason@lowepower.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2513677Sjason@lowepower.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2613677Sjason@lowepower.com# 2713677Sjason@lowepower.com# Authors: Ron Dreslinski 2813677Sjason@lowepower.com 2913677Sjason@lowepower.comimport m5 3013677Sjason@lowepower.comfrom m5.objects import * 3113677Sjason@lowepower.comm5.util.addToPath('../../../configs/') 3213677Sjason@lowepower.comfrom common.Caches import * 3313677Sjason@lowepower.com 3413677Sjason@lowepower.com#MAX CORES IS 8 with the fals sharing method 3513677Sjason@lowepower.comnb_cores = 8 3613677Sjason@lowepower.comcpus = [MemTest(max_loads = 1e5, progress_interval = 1e4) 3713677Sjason@lowepower.com for i in xrange(nb_cores) ] 3813677Sjason@lowepower.com 3913677Sjason@lowepower.com# system simulated 4013677Sjason@lowepower.comsystem = System(cpu = cpus, 4113677Sjason@lowepower.com physmem = SimpleMemory(), 4213677Sjason@lowepower.com membus = SystemXBar()) 4313677Sjason@lowepower.com# Dummy voltage domain for all our clock domains 4413677Sjason@lowepower.comsystem.voltage_domain = VoltageDomain() 4513677Sjason@lowepower.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 4613677Sjason@lowepower.com voltage_domain = system.voltage_domain) 4713677Sjason@lowepower.com 4813677Sjason@lowepower.com# Create a seperate clock domain for components that should run at 4913677Sjason@lowepower.com# CPUs frequency 5013677Sjason@lowepower.comsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 5113677Sjason@lowepower.com voltage_domain = system.voltage_domain) 5213677Sjason@lowepower.com 5313677Sjason@lowepower.comsystem.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) 5413677Sjason@lowepower.comsystem.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 5513677Sjason@lowepower.comsystem.l2c.cpu_side = system.toL2Bus.master 5613677Sjason@lowepower.com 5713677Sjason@lowepower.com# connect l2c to membus 5813677Sjason@lowepower.comsystem.l2c.mem_side = system.membus.slave 5913677Sjason@lowepower.com 6013677Sjason@lowepower.com# add L1 caches 6113677Sjason@lowepower.comfor cpu in cpus: 6213677Sjason@lowepower.com # All cpus are associated with cpu_clk_domain 6313677Sjason@lowepower.com cpu.clk_domain = system.cpu_clk_domain 6413677Sjason@lowepower.com cpu.l1c = L1Cache(size = '32kB', assoc = 4) 6513677Sjason@lowepower.com cpu.l1c.cpu_side = cpu.port 6613677Sjason@lowepower.com cpu.l1c.mem_side = system.toL2Bus.slave 6713677Sjason@lowepower.com 6813677Sjason@lowepower.comsystem.system_port = system.membus.slave 6913677Sjason@lowepower.com 7013677Sjason@lowepower.com# connect memory to membus 7113677Sjason@lowepower.comsystem.physmem.port = system.membus.master 7213677Sjason@lowepower.com 7313677Sjason@lowepower.com 7413677Sjason@lowepower.com# ----------------------- 7513677Sjason@lowepower.com# run simulation 7613677Sjason@lowepower.com# ----------------------- 7713677Sjason@lowepower.com 7813677Sjason@lowepower.comroot = Root( full_system = False, system = system ) 7913677Sjason@lowepower.comroot.system.mem_mode = 'timing' 8013677Sjason@lowepower.com 8113677Sjason@lowepower.comm5.instantiate() 8213677Sjason@lowepower.comexit_event = m5.simulate() 8313677Sjason@lowepower.comif exit_event.getCause() != "maximum number of loads reached": 8413677Sjason@lowepower.com exit(1) 8513677Sjason@lowepower.com 86