112610Sjason@lowepower.com# -*- coding: utf-8 -*- 212610Sjason@lowepower.com# Copyright (c) 2015 Jason Power 312610Sjason@lowepower.com# All rights reserved. 412610Sjason@lowepower.com# 512610Sjason@lowepower.com# Redistribution and use in source and binary forms, with or without 612610Sjason@lowepower.com# modification, are permitted provided that the following conditions are 712610Sjason@lowepower.com# met: redistributions of source code must retain the above copyright 812610Sjason@lowepower.com# notice, this list of conditions and the following disclaimer; 912610Sjason@lowepower.com# redistributions in binary form must reproduce the above copyright 1012610Sjason@lowepower.com# notice, this list of conditions and the following disclaimer in the 1112610Sjason@lowepower.com# documentation and/or other materials provided with the distribution; 1212610Sjason@lowepower.com# neither the name of the copyright holders nor the names of its 1312610Sjason@lowepower.com# contributors may be used to endorse or promote products derived from 1412610Sjason@lowepower.com# this software without specific prior written permission. 1512610Sjason@lowepower.com# 1612610Sjason@lowepower.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712610Sjason@lowepower.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812610Sjason@lowepower.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912610Sjason@lowepower.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012610Sjason@lowepower.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112610Sjason@lowepower.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212610Sjason@lowepower.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312610Sjason@lowepower.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412610Sjason@lowepower.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512610Sjason@lowepower.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612610Sjason@lowepower.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712610Sjason@lowepower.com# 2812610Sjason@lowepower.com# Authors: Jason Lowe-Power 2912610Sjason@lowepower.com 3012610Sjason@lowepower.com""" This file creates a system with Ruby caches and runs the ruby random tester 3112610Sjason@lowepower.comSee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 3212610Sjason@lowepower.com 3312610Sjason@lowepower.comIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 3412610Sjason@lowepower.com also needs to be updated. For now, email Jason <jason@lowepower.com> 3512610Sjason@lowepower.com 3612610Sjason@lowepower.com""" 3712610Sjason@lowepower.comfrom __future__ import print_function 3813774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 3912610Sjason@lowepower.com 4012610Sjason@lowepower.com# import the m5 (gem5) library created when gem5 is built 4112610Sjason@lowepower.comimport m5 4212610Sjason@lowepower.com# import all of the SimObjects 4312610Sjason@lowepower.comfrom m5.objects import * 4412610Sjason@lowepower.com 4513840Sjason@lowepower.comfrom test_caches import TestCacheSystem 4612610Sjason@lowepower.com 4712610Sjason@lowepower.com# create the system we are going to simulate 4812610Sjason@lowepower.comsystem = System() 4912610Sjason@lowepower.com 5012610Sjason@lowepower.com# Set the clock fequency of the system (and all of its children) 5112610Sjason@lowepower.comsystem.clk_domain = SrcClockDomain() 5212610Sjason@lowepower.comsystem.clk_domain.clock = '1GHz' 5312610Sjason@lowepower.comsystem.clk_domain.voltage_domain = VoltageDomain() 5412610Sjason@lowepower.com 5512610Sjason@lowepower.com# Set up the system 5612610Sjason@lowepower.comsystem.mem_mode = 'timing' # Use timing accesses 5712610Sjason@lowepower.comsystem.mem_ranges = [AddrRange('512MB')] # Create an address range 5812610Sjason@lowepower.com 5912610Sjason@lowepower.com# Create the tester 6012610Sjason@lowepower.comsystem.tester = RubyTester(checks_to_complete = 100, 6112610Sjason@lowepower.com wakeup_frequency = 10, 6212610Sjason@lowepower.com num_cpus = 2) 6312610Sjason@lowepower.com 6413842Sjason@lowepower.com# Create a simple memory controller and connect it to the membus 6513842Sjason@lowepower.comsystem.mem_ctrl = SimpleMemory(latency="50ns", bandwidth="0GB/s") 6612610Sjason@lowepower.comsystem.mem_ctrl.range = system.mem_ranges[0] 6712610Sjason@lowepower.com 6812610Sjason@lowepower.com# Create the Ruby System 6912610Sjason@lowepower.comsystem.caches = TestCacheSystem() 7012610Sjason@lowepower.comsystem.caches.setup(system, system.tester, [system.mem_ctrl]) 7112610Sjason@lowepower.com 7212610Sjason@lowepower.com# set up the root SimObject and start the simulation 7312610Sjason@lowepower.comroot = Root(full_system = False, system = system) 7412610Sjason@lowepower.com 7512610Sjason@lowepower.com# Not much point in this being higher than the L1 latency 7612610Sjason@lowepower.comm5.ticks.setGlobalFrequency('1ns') 7712610Sjason@lowepower.com 7812610Sjason@lowepower.com# instantiate all of the objects we've created above 7912610Sjason@lowepower.comm5.instantiate() 8012610Sjason@lowepower.com 8112610Sjason@lowepower.comprint("Beginning simulation!") 8212610Sjason@lowepower.comexit_event = m5.simulate() 8312610Sjason@lowepower.comprint('Exiting @ tick {} because {}'.format( 8412610Sjason@lowepower.com m5.curTick(), exit_event.getCause()) 8512610Sjason@lowepower.com ) 86