xref: /gem5/tests/configs/tgen-simple-mem.py

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# Authors: Andreas Hansson

import m5
from m5.objects import *

# both traffic generator and communication monitor are only available
# if we have protobuf support, so potentially skip this test
require_sim_object("TrafficGen")
require_sim_object("CommMonitor")

# even if this is only a traffic generator, call it cpu to make sure
# the scripts are happy
cpu = TrafficGen(
    config_file=srcpath("tests/quick/se/70.tgen/tgen-simple-mem.cfg"))

# system simulated
system = System(cpu = cpu, physmem = SimpleMemory(),
                membus = IOXBar(width = 16),
                clk_domain = SrcClockDomain(clock = '1GHz',
                                            voltage_domain =
                                            VoltageDomain()))

# add a communication monitor, and also trace all the packets and
# calculate and verify stack distance
system.monitor = CommMonitor()
system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
system.monitor.stackdist = StackDistProbe(verify = True)

# connect the traffic generator to the bus via a communication monitor
system.cpu.port = system.monitor.slave
system.monitor.master = system.membus.slave

# connect the system port even if it is not used in this example
system.system_port = system.membus.slave

# connect memory to the membus
system.physmem.port = system.membus.master

# -----------------------
# run simulation
# -----------------------

root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'