1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31
32nb_cores = 4
33cpus = [ DerivO3CPU(cpu_id=i) for i in range(nb_cores) ]
34
35import ruby_config
36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
37
38# system simulated
39system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
40                mem_mode = "timing",
41                clk_domain = SrcClockDomain(clock = '1GHz'))
42
43# Create a seperate clock domain for components that should run at
44# CPUs frequency
45system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
46
47for cpu in cpus:
48    # create the interrupt controller
49    cpu.createInterruptController()
50    cpu.connectAllPorts(system.membus)
51    # All cpus are associated with cpu_clk_domain
52    cpu.clk_domain = system.cpu_clk_domain
53
54# connect memory to membus
55system.physmem.port = system.membus.master
56
57# Connect the system port for loading of binaries etc
58system.system_port = system.membus.slave
59
60# -----------------------
61# run simulation
62# -----------------------
63
64root = Root(full_system = False, system = system)
65root.system.mem_mode = 'timing'
66