16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 26928SBrad.Beckmann@amd.com# Copyright (c) 2010 Advanced Micro Devices, Inc. 36166Ssteve.reinhardt@amd.com# All rights reserved. 46166Ssteve.reinhardt@amd.com# 56166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without 66166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are 76166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright 86166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer; 96166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright 106166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the 116166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution; 126166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its 136166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from 146166Ssteve.reinhardt@amd.com# this software without specific prior written permission. 156166Ssteve.reinhardt@amd.com# 166166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206166Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216166Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226166Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236166Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246166Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276166Ssteve.reinhardt@amd.com# 286166Ssteve.reinhardt@amd.com# Authors: Ron Dreslinski 296166Ssteve.reinhardt@amd.com 306166Ssteve.reinhardt@amd.comimport m5 316166Ssteve.reinhardt@amd.comfrom m5.objects import * 326919SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 336919SBrad.Beckmann@amd.comfrom m5.util import addToPath 346919SBrad.Beckmann@amd.comimport os, optparse, sys 356166Ssteve.reinhardt@amd.com 3611670Sandreas.hansson@arm.comm5.util.addToPath('../configs/') 376919SBrad.Beckmann@amd.com 3811670Sandreas.hansson@arm.comfrom ruby import Ruby 3911682Sandreas.hansson@arm.comfrom common import Options 406919SBrad.Beckmann@amd.com 416919SBrad.Beckmann@amd.comparser = optparse.OptionParser() 428920Snilay@cs.wisc.eduOptions.addCommonOptions(parser) 436919SBrad.Beckmann@amd.com 447570SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 457570SBrad.Beckmann@amd.comRuby.define_options(parser) 466919SBrad.Beckmann@amd.com 476919SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 486166Ssteve.reinhardt@amd.com 497570SBrad.Beckmann@amd.com# 507570SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 517570SBrad.Beckmann@amd.com# races between requests and writebacks. 527570SBrad.Beckmann@amd.com# 537570SBrad.Beckmann@amd.comoptions.l1d_size="256B" 547570SBrad.Beckmann@amd.comoptions.l1i_size="256B" 557570SBrad.Beckmann@amd.comoptions.l2_size="512B" 567570SBrad.Beckmann@amd.comoptions.l3_size="1kB" 577570SBrad.Beckmann@amd.comoptions.l1d_assoc=2 587570SBrad.Beckmann@amd.comoptions.l1i_assoc=2 597570SBrad.Beckmann@amd.comoptions.l2_assoc=2 607570SBrad.Beckmann@amd.comoptions.l3_assoc=2 619841Snilay@cs.wisc.eduoptions.ports=32 627570SBrad.Beckmann@amd.com 636166Ssteve.reinhardt@amd.com#MAX CORES IS 8 with the fals sharing method 646166Ssteve.reinhardt@amd.comnb_cores = 8 656928SBrad.Beckmann@amd.com 666928SBrad.Beckmann@amd.com# ruby does not support atomic, functional, or uncacheable accesses 6710688Sandreas.hansson@arm.comcpus = [ MemTest(percent_functional=50, 688436SBrad.Beckmann@amd.com percent_uncacheable=0, suppress_func_warnings=True) \ 6913718Sandreas.sandberg@arm.com for i in range(nb_cores) ] 706166Ssteve.reinhardt@amd.com 716919SBrad.Beckmann@amd.com# overwrite options.num_cpus with the nb_cores value 726919SBrad.Beckmann@amd.comoptions.num_cpus = nb_cores 7311320Ssteve.reinhardt@amd.com 746919SBrad.Beckmann@amd.com# system simulated 7510688Sandreas.hansson@arm.comsystem = System(cpu = cpus) 769827Sakash.bagdia@arm.com# Dummy voltage domain for all our clock domains 779827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain() 789827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz', 799827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 809793Sakash.bagdia@arm.com 819793Sakash.bagdia@arm.com# Create a seperate clock domain for components that should run at 829793Sakash.bagdia@arm.com# CPUs frequency 839827Sakash.bagdia@arm.comsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 849827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 859793Sakash.bagdia@arm.com 869793Sakash.bagdia@arm.com# All cpus are associated with cpu_clk_domain 879793Sakash.bagdia@arm.comfor cpu in cpus: 889793Sakash.bagdia@arm.com cpu.clk_domain = system.cpu_clk_domain 896289Snate@binkert.org 909826Sandreas.hansson@arm.comsystem.mem_ranges = AddrRange('256MB') 919826Sandreas.hansson@arm.com 9210519Snilay@cs.wisc.eduRuby.create_system(options, False, system) 936166Ssteve.reinhardt@amd.com 949793Sakash.bagdia@arm.com# Create a separate clock domain for Ruby 959827Sakash.bagdia@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 969827Sakash.bagdia@arm.com voltage_domain = system.voltage_domain) 979793Sakash.bagdia@arm.com 9810120Snilay@cs.wisc.eduassert(len(cpus) == len(system.ruby._cpu_ports)) 996166Ssteve.reinhardt@amd.com 10010120Snilay@cs.wisc.edufor (i, ruby_port) in enumerate(system.ruby._cpu_ports): 1016919SBrad.Beckmann@amd.com # 10210688Sandreas.hansson@arm.com # Tie the cpu port to the ruby cpu ports and 1036919SBrad.Beckmann@amd.com # physmem, respectively 1046919SBrad.Beckmann@amd.com # 10510688Sandreas.hansson@arm.com cpus[i].port = ruby_port.slave 10610688Sandreas.hansson@arm.com 1077938SBrad.Beckmann@amd.com # 1087938SBrad.Beckmann@amd.com # Since the memtester is incredibly bursty, increase the deadlock 1097938SBrad.Beckmann@amd.com # threshold to 1 million cycles 1107938SBrad.Beckmann@amd.com # 1117938SBrad.Beckmann@amd.com ruby_port.deadlock_threshold = 1000000 1126166Ssteve.reinhardt@amd.com 1136166Ssteve.reinhardt@amd.com# ----------------------- 1146166Ssteve.reinhardt@amd.com# run simulation 1156166Ssteve.reinhardt@amd.com# ----------------------- 1166166Ssteve.reinhardt@amd.com 1178801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system) 1186166Ssteve.reinhardt@amd.comroot.system.mem_mode = 'timing' 119