xref: /gem5/util/tlm/conf/tlm_master.py

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# Authors: Christian Menard
#

import m5
from m5.objects import *

import os

# Base System Architecture:
#         +-----+           ^
#         | TLM |           | TLM World
#         +--+--+           | (see main.cc)
#            |              v
# +----------v-----------+  External Port (see sc_master_port.*)
# |        Membus        |  ^
# +----------+-----------+  |
#            |              | gem5 World
#        +---v----+         |
#        | Memory |         |
#        +--------+         v
#

# Create a system with a Crossbar and a simple Memory:
system = System()
system.membus = IOXBar(width = 16)
system.physmem = SimpleMemory(range = AddrRange('512MB'))
system.clk_domain = SrcClockDomain(clock = '1.5GHz',
    voltage_domain = VoltageDomain(voltage = '1V'))

# Create a external TLM port:
system.tlm = ExternalMaster()
system.tlm.port_type = "tlm_master"
system.tlm.port_data = "transactor"

# Route the connections:
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
system.tlm.port = system.membus.slave
system.mem_mode = 'timing'

# Start the simulation:
root = Root(full_system = False, system = system)
m5.instantiate()
m5.simulate()