1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * Copyright (c) 2013 Cornell University 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Vasileios Spiliopoulos 39 * Akash Bagdia 40 * Andreas Hansson 41 * Christopher Torng 42 * Stephan Diestelhorst 43 */ 44 45#include "sim/clock_domain.hh" 46 47#include <algorithm> 48#include <functional> 49 50#include "base/trace.hh" 51#include "debug/ClockDomain.hh" 52#include "params/ClockDomain.hh" 53#include "params/DerivedClockDomain.hh" 54#include "params/SrcClockDomain.hh" 55#include "sim/clocked_object.hh" 56#include "sim/voltage_domain.hh" 57 58void 59ClockDomain::regStats() 60{ 61 SimObject::regStats(); 62 63 using namespace Stats; 64 65 // Expose the current clock period as a stat for observability in 66 // the dumps 67 currentClock 68 .scalar(_clockPeriod) 69 .name(params()->name + ".clock") 70 .desc("Clock period in ticks") 71 ; 72} 73 74double 75ClockDomain::voltage() const 76{ 77 return _voltageDomain->voltage(); 78} 79 80SrcClockDomain::SrcClockDomain(const Params *p) : 81 ClockDomain(p, p->voltage_domain), 82 freqOpPoints(p->clock), 83 _domainID(p->domain_id), 84 _perfLevel(p->init_perf_level) 85{ 86 VoltageDomain *vdom = p->voltage_domain; 87 88 fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\ 89 "domain %d %s\n", _domainID, name()); 90 91 fatal_if(!vdom, "DVFS: Empty voltage domain specified for "\ 92 "domain %d %s\n", _domainID, name()); 93 94 fatal_if((vdom->numVoltages() > 1) && 95 (vdom->numVoltages() != freqOpPoints.size()), 96 "DVFS: Number of frequency and voltage scaling points do "\ 97 "not match: %d:%d ID: %d %s.\n", vdom->numVoltages(), 98 freqOpPoints.size(), _domainID, name()); 99 100 // Frequency (& voltage) points should be declared in descending order, 101 // NOTE: Frequency is inverted to ticks, so checking for ascending ticks 102 fatal_if(!std::is_sorted(freqOpPoints.begin(), freqOpPoints.end()), 103 "DVFS: Frequency operation points not in descending order for "\ 104 "domain with ID %d\n", _domainID); 105 106 fatal_if(_perfLevel >= freqOpPoints.size(), "DVFS: Initial DVFS point %d "\ 107 "is outside of list for Domain ID: %d\n", _perfLevel, _domainID); 108 109 clockPeriod(freqOpPoints[_perfLevel]); 110 111 vdom->registerSrcClockDom(this); 112} 113 114void 115SrcClockDomain::clockPeriod(Tick clock_period) 116{ 117 if (clock_period == 0) { 118 fatal("%s has a clock period of zero\n", name()); 119 } 120 121 // Align all members to the current tick 122 for (auto m = members.begin(); m != members.end(); ++m) { 123 (*m)->updateClockPeriod(); 124 } 125 126 _clockPeriod = clock_period; 127 128 DPRINTF(ClockDomain, 129 "Setting clock period to %d ticks for source clock %s\n", 130 _clockPeriod, name()); 131 132 // inform any derived clocks they need to updated their period 133 for (auto c = children.begin(); c != children.end(); ++c) { 134 (*c)->updateClockPeriod(); 135 } 136} 137 138void 139SrcClockDomain::perfLevel(PerfLevel perf_level) 140{ 141 assert(validPerfLevel(perf_level)); 142 143 if (perf_level == _perfLevel) { 144 // Silently ignore identical overwrites 145 return; 146 } 147 148 DPRINTF(ClockDomain, "DVFS: Switching performance level of domain %s "\ 149 "(id: %d) from %d to %d\n", name(), domainID(), _perfLevel, 150 perf_level); 151 152 _perfLevel = perf_level; 153 154 signalPerfLevelUpdate(); 155} 156 157void SrcClockDomain::signalPerfLevelUpdate() 158{ 159 // Signal the voltage domain that we have changed our perf level so that the 160 // voltage domain can recompute its performance level 161 voltageDomain()->sanitiseVoltages(); 162 163 // Integrated switching of the actual clock value, too 164 clockPeriod(clkPeriodAtPerfLevel()); 165} 166 167void 168SrcClockDomain::serialize(CheckpointOut &cp) const 169{ 170 SERIALIZE_SCALAR(_perfLevel); 171 ClockDomain::serialize(cp); 172} 173 174void 175SrcClockDomain::unserialize(CheckpointIn &cp) 176{ 177 ClockDomain::unserialize(cp); 178 UNSERIALIZE_SCALAR(_perfLevel); 179} 180 181void 182SrcClockDomain::startup() 183{ 184 // Perform proper clock update when all related components have been 185 // created (i.e. after unserialization / object creation) 186 signalPerfLevelUpdate(); 187} 188 189SrcClockDomain * 190SrcClockDomainParams::create() 191{ 192 return new SrcClockDomain(this); 193} 194 195DerivedClockDomain::DerivedClockDomain(const Params *p) : 196 ClockDomain(p, p->clk_domain->voltageDomain()), 197 parent(*p->clk_domain), 198 clockDivider(p->clk_divider) 199{ 200 // Ensure that clock divider setting works as frequency divider and never 201 // work as frequency multiplier 202 if (clockDivider < 1) { 203 fatal("Clock divider param cannot be less than 1"); 204 } 205 206 // let the parent keep track of this derived domain so that it can 207 // propagate changes 208 parent.addDerivedDomain(this); 209 210 // update our clock period based on the parents clock 211 updateClockPeriod(); 212} 213 214void 215DerivedClockDomain::updateClockPeriod() 216{ 217 // Align all members to the current tick 218 for (auto m = members.begin(); m != members.end(); ++m) { 219 (*m)->updateClockPeriod(); 220 } 221 222 // recalculate the clock period, relying on the fact that changes 223 // propagate downwards in the tree 224 _clockPeriod = parent.clockPeriod() * clockDivider; 225 226 DPRINTF(ClockDomain, 227 "Setting clock period to %d ticks for derived clock %s\n", 228 _clockPeriod, name()); 229 230 // inform any derived clocks 231 for (auto c = children.begin(); c != children.end(); ++c) { 232 (*c)->updateClockPeriod(); 233 } 234} 235 236DerivedClockDomain * 237DerivedClockDomainParams::create() 238{ 239 return new DerivedClockDomain(this); 240} 241