Searched refs:physmem (Results 1 - 25 of 25) sorted by relevance

/gem5/tests/long/se/10.mcf/
H A Dtest.py34 root.system.physmem.range=AddrRange('256MB')
/gem5/tests/quick/se/10.mcf/
H A Dtest.py34 root.system.physmem.range=AddrRange('256MB')
/gem5/tests/configs/
H A Dt1000-simple-atomic.py51 # the physmem name to avoid bumping all the reference stats
52 system.physmem = [SimpleMemory(range = r)
54 for i in range(len(system.physmem)):
55 system.physmem[i].port = system.membus.master
H A Do3-timing-ruby.py38 physmem = ruby_memory, variable
47 system.physmem.port = system.membus.master
H A Dtgen-simple-mem.py52 system = System(cpu = cpu, physmem = SimpleMemory(),
72 system.physmem.port = system.membus.master
H A Dtgen-dram-ctrl.py52 system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
69 system.physmem.port = system.membus.master
H A Do3-timing-mp-ruby.py39 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
55 system.physmem.port = system.membus.master
H A Dsimple-atomic-mp-ruby.py39 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
53 system.physmem.port = system.membus.master
H A Dtwosys-tsunami-simple-atomic.py68 test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0])
69 test_sys.physmem.port = test_sys.membus.master
100 drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0])
101 drive_sys.physmem.port = drive_sys.membus.master
H A Dmemtest.py40 physmem = SimpleMemory(), variable
70 system.physmem.port = system.membus.master
H A Dmemtest-filter.py40 physmem = SimpleMemory(), variable
71 system.physmem.port = system.membus.master
H A Dbase_config.py227 system = System(physmem = self.mem_class(),
233 system.physmem.port = system.membus.master
278 # the physmem name to avoid bumping all the reference stats
279 system.physmem = [self.mem_class(range = r)
291 for i in range(len(system.physmem)):
292 system.physmem[i].port = system.llc[i].mem_side
/gem5/util/tlm/conf/
H A Dtlm_master.py57 system.physmem = SimpleMemory(range = AddrRange('512MB'))
68 system.physmem.port = system.membus.master
H A Dtlm_slave.py58 system.physmem = SimpleMemory() # This must be instanciated, even if not needed
H A Dtlm_elastic_slave.py104 system.physmem = SimpleMemory() # This must be instantiated, even if not needed
/gem5/tests/gem5/memory/
H A Dmemtest-run.py41 physmem = SimpleMemory(), variable
71 system.physmem.port = system.membus.master
H A Dsimple-run.py68 system = System(cpu = cpu, physmem = MyMem(),
88 system.physmem.port = system.membus.master
/gem5/src/sim/
H A Dsystem.cc106 physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve),
390 if ((pagePtr << PageShift) > physmem.totalSize())
398 return physmem.totalSize();
404 return physmem.totalSize() - (pagePtr << PageShift);
410 return physmem.isMemAddr(addr);
428 physmem.serializeSection(cp, "physmem");
441 physmem.unserializeSection(cp, "physmem");
[all...]
H A Dsystem.hh268 PhysicalMemory& getPhysMem() { return physmem; }
309 PhysicalMemory physmem; member in class:System
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py112 system.physmem = SimpleMemory() # This must be instantiated, even if not needed
/gem5/configs/example/
H A Dmemtest.py226 system = System(physmem = SimpleMemory(),
315 system.llc.mem_side = system.physmem.port
317 last_subsys.xbar.master = system.physmem.port
H A Dmemcheck.py222 system = System(physmem = DDR3_1600_8x8())
302 last_subsys.xbar.master = system.physmem.port
/gem5/configs/splash2/
H A Drun.py199 system = System(cpu = cpus, physmem = SimpleMemory(),
210 system.physmem.port = system.membus.master
H A Dcluster.py214 physmem = SimpleMemory(), variable
225 system.physmem.port = system.membus.master
/gem5/src/arch/arm/linux/
H A Dsystem.cc175 AddrRangeList atagRanges = physmem.getConfAddrRanges();

Completed in 36 milliseconds