12689Sktlim@umich.edu/* 212680Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2014,2017-2018 ARM Limited 38666SPrakash.Ramrakhyani@arm.com * All rights reserved 48666SPrakash.Ramrakhyani@arm.com * 58666SPrakash.Ramrakhyani@arm.com * The license below extends only to copyright in the software and shall 68666SPrakash.Ramrakhyani@arm.com * not be construed as granting a license to any other intellectual 78666SPrakash.Ramrakhyani@arm.com * property including but not limited to intellectual property relating 88666SPrakash.Ramrakhyani@arm.com * to a hardware implementation of the functionality of the software 98666SPrakash.Ramrakhyani@arm.com * licensed hereunder. You may use the software subject to the license 108666SPrakash.Ramrakhyani@arm.com * terms below provided that you ensure that this notice is replicated 118666SPrakash.Ramrakhyani@arm.com * unmodified and in its entirety in all distributions of the software, 128666SPrakash.Ramrakhyani@arm.com * modified or unmodified, in source code or in binary form. 138666SPrakash.Ramrakhyani@arm.com * 142689Sktlim@umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162689Sktlim@umich.edu * All rights reserved. 172689Sktlim@umich.edu * 182689Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 192689Sktlim@umich.edu * modification, are permitted provided that the following conditions are 202689Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 212689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 222689Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 232689Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 242689Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 252689Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 262689Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 272689Sktlim@umich.edu * this software without specific prior written permission. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302689Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312689Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322689Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332689Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342689Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352689Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362689Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372689Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382689Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392689Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Steve Reinhardt 422689Sktlim@umich.edu * Lisa Hsu 432689Sktlim@umich.edu * Nathan Binkert 442689Sktlim@umich.edu * Ali Saidi 457897Shestness@cs.utexas.edu * Rick Strong 462689Sktlim@umich.edu */ 472689Sktlim@umich.edu 4811793Sbrandon.potter@amd.com#include "sim/system.hh" 4911793Sbrandon.potter@amd.com 5012515Sgiacomo.travaglini@arm.com#include <algorithm> 5112515Sgiacomo.travaglini@arm.com 523960Sgblack@eecs.umich.edu#include "arch/remote_gdb.hh" 534194Ssaidi@eecs.umich.edu#include "arch/utility.hh" 541070SN/A#include "base/loader/object_file.hh" 551070SN/A#include "base/loader/symtab.hh" 569142Ssteve.reinhardt@amd.com#include "base/str.hh" 572521SN/A#include "base/trace.hh" 5811839SCurtis.Dunham@arm.com#include "config/use_kvm.hh" 5911839SCurtis.Dunham@arm.com#if USE_KVM 6012100SCurtis.Dunham@arm.com#include "cpu/kvm/base.hh" 6111839SCurtis.Dunham@arm.com#include "cpu/kvm/vm.hh" 6211839SCurtis.Dunham@arm.com#endif 6312122Sjose.marinho@arm.com#include "cpu/base.hh" 648229Snate@binkert.org#include "cpu/thread_context.hh" 658232Snate@binkert.org#include "debug/Loader.hh" 668666SPrakash.Ramrakhyani@arm.com#include "debug/WorkItems.hh" 679293Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 682522SN/A#include "mem/physical.hh" 698769Sgblack@eecs.umich.edu#include "params/System.hh" 702037SN/A#include "sim/byteswap.hh" 718229Snate@binkert.org#include "sim/debug.hh" 728769Sgblack@eecs.umich.edu#include "sim/full_system.hh" 7313883Sdavid.hashe@amd.com#include "sim/redirect_path.hh" 746658Snate@binkert.org 7510494Sandreas.hansson@arm.com/** 7610494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 7710494Sandreas.hansson@arm.com * actually have a definition. 7810494Sandreas.hansson@arm.com */ 7910494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 8010494Sandreas.hansson@arm.com#include "kern/kernel_stats.hh" 8111793Sbrandon.potter@amd.com 8210494Sandreas.hansson@arm.com#endif 8310494Sandreas.hansson@arm.com 842SN/Ausing namespace std; 852107SN/Ausing namespace TheISA; 862SN/A 872SN/Avector<System *> System::systemList; 882SN/A 892SN/Aint System::numSystemsRunning = 0; 902SN/A 911070SN/ASystem::System(Params *p) 9213892Sgabeblack@google.com : SimObject(p), _systemPort("system_port", this), 9311146Smitch.hayenga@arm.com multiThread(p->multi_thread), 948826Snilay@cs.wisc.edu pagePtr(0), 952521SN/A init_param(p->init_param), 969814Sandreas.hansson@arm.com physProxy(_systemPort, p->cache_line_size), 9710360Sandreas.hansson@arm.com kernelSymtab(nullptr), 9810360Sandreas.hansson@arm.com kernel(nullptr), 997580SAli.Saidi@arm.com loadAddrMask(p->load_addr_mask), 10010037SARM gem5 Developers loadAddrOffset(p->load_offset), 10111839SCurtis.Dunham@arm.com#if USE_KVM 10211839SCurtis.Dunham@arm.com kvmVM(p->kvm_vm), 10311839SCurtis.Dunham@arm.com#else 10411839SCurtis.Dunham@arm.com kvmVM(nullptr), 10511839SCurtis.Dunham@arm.com#endif 10610700Sandreas.hansson@arm.com physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve), 1077914SBrad.Beckmann@amd.com memoryMode(p->mem_mode), 1089814Sandreas.hansson@arm.com _cacheLineSize(p->cache_line_size), 1097914SBrad.Beckmann@amd.com workItemsBegin(0), 1107914SBrad.Beckmann@amd.com workItemsEnd(0), 1118666SPrakash.Ramrakhyani@arm.com numWorkIds(p->num_work_ids), 11211420Sdavid.guillen@arm.com thermalModel(p->thermal_model), 1137914SBrad.Beckmann@amd.com _params(p), 1148666SPrakash.Ramrakhyani@arm.com totalNumInsts(0), 11513883Sdavid.hashe@amd.com instEventQueue("system instruction-based event queue"), 11613883Sdavid.hashe@amd.com redirectPaths(p->redirect_paths) 1172SN/A{ 11813883Sdavid.hashe@amd.com 1191070SN/A // add self to global system list 1201070SN/A systemList.push_back(this); 1211070SN/A 12211839SCurtis.Dunham@arm.com#if USE_KVM 12311839SCurtis.Dunham@arm.com if (kvmVM) { 12411839SCurtis.Dunham@arm.com kvmVM->setSystem(this); 12511839SCurtis.Dunham@arm.com } 12611839SCurtis.Dunham@arm.com#endif 12711839SCurtis.Dunham@arm.com 1288769Sgblack@eecs.umich.edu if (FullSystem) { 1298769Sgblack@eecs.umich.edu kernelSymtab = new SymbolTable; 1308769Sgblack@eecs.umich.edu if (!debugSymbolTable) 1318769Sgblack@eecs.umich.edu debugSymbolTable = new SymbolTable; 1328666SPrakash.Ramrakhyani@arm.com } 1338832SAli.Saidi@ARM.com 1349814Sandreas.hansson@arm.com // check if the cache line size is a value known to work 1359814Sandreas.hansson@arm.com if (!(_cacheLineSize == 16 || _cacheLineSize == 32 || 1369814Sandreas.hansson@arm.com _cacheLineSize == 64 || _cacheLineSize == 128)) 1379814Sandreas.hansson@arm.com warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n"); 1389814Sandreas.hansson@arm.com 1398832SAli.Saidi@ARM.com // Get the generic system master IDs 1408832SAli.Saidi@ARM.com MasterID tmp_id M5_VAR_USED; 14112680Sgiacomo.travaglini@arm.com tmp_id = getMasterId(this, "writebacks"); 1428832SAli.Saidi@ARM.com assert(tmp_id == Request::wbMasterId); 14312680Sgiacomo.travaglini@arm.com tmp_id = getMasterId(this, "functional"); 1448832SAli.Saidi@ARM.com assert(tmp_id == Request::funcMasterId); 14512680Sgiacomo.travaglini@arm.com tmp_id = getMasterId(this, "interrupt"); 1468832SAli.Saidi@ARM.com assert(tmp_id == Request::intMasterId); 1478832SAli.Saidi@ARM.com 1488885SAli.Saidi@ARM.com if (FullSystem) { 1498885SAli.Saidi@ARM.com if (params()->kernel == "") { 1508885SAli.Saidi@ARM.com inform("No kernel set for full system simulation. " 1519147Snilay@cs.wisc.edu "Assuming you know what you're doing\n"); 1528885SAli.Saidi@ARM.com } else { 1538885SAli.Saidi@ARM.com // Get the kernel code 1548885SAli.Saidi@ARM.com kernel = createObjectFile(params()->kernel); 1558885SAli.Saidi@ARM.com inform("kernel located at: %s", params()->kernel); 1568885SAli.Saidi@ARM.com 1578885SAli.Saidi@ARM.com if (kernel == NULL) 1588885SAli.Saidi@ARM.com fatal("Could not load kernel file %s", params()->kernel); 1598885SAli.Saidi@ARM.com 1608885SAli.Saidi@ARM.com // setup entry points 1618885SAli.Saidi@ARM.com kernelStart = kernel->textBase(); 1628885SAli.Saidi@ARM.com kernelEnd = kernel->bssBase() + kernel->bssSize(); 1638885SAli.Saidi@ARM.com kernelEntry = kernel->entryPoint(); 1648885SAli.Saidi@ARM.com 16512272SGeoffrey.Blake@arm.com // If load_addr_mask is set to 0x0, then auto-calculate 16612272SGeoffrey.Blake@arm.com // the smallest mask to cover all kernel addresses so gem5 16712272SGeoffrey.Blake@arm.com // can relocate the kernel to a new offset. 16812272SGeoffrey.Blake@arm.com if (loadAddrMask == 0) { 16912272SGeoffrey.Blake@arm.com Addr shift_amt = findMsbSet(kernelEnd - kernelStart) + 1; 17012272SGeoffrey.Blake@arm.com loadAddrMask = ((Addr)1 << shift_amt) - 1; 17112272SGeoffrey.Blake@arm.com } 17212272SGeoffrey.Blake@arm.com 1738885SAli.Saidi@ARM.com // load symbols 1748885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(kernelSymtab)) 1758885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1768885SAli.Saidi@ARM.com 1778885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(kernelSymtab)) 1788885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1798885SAli.Saidi@ARM.com 1808885SAli.Saidi@ARM.com if (!kernel->loadGlobalSymbols(debugSymbolTable)) 1818885SAli.Saidi@ARM.com fatal("could not load kernel symbols\n"); 1828885SAli.Saidi@ARM.com 1838885SAli.Saidi@ARM.com if (!kernel->loadLocalSymbols(debugSymbolTable)) 1848885SAli.Saidi@ARM.com fatal("could not load kernel local symbols\n"); 1858885SAli.Saidi@ARM.com 1868885SAli.Saidi@ARM.com // Loading only needs to happen once and after memory system is 1878885SAli.Saidi@ARM.com // connected so it will happen in initState() 1888885SAli.Saidi@ARM.com } 18912262Sandreas.sandberg@arm.com 19012262Sandreas.sandberg@arm.com for (const auto &obj_name : p->kernel_extras) { 19112262Sandreas.sandberg@arm.com inform("Loading additional kernel object: %s", obj_name); 19212262Sandreas.sandberg@arm.com ObjectFile *obj = createObjectFile(obj_name); 19312262Sandreas.sandberg@arm.com fatal_if(!obj, "Failed to additional kernel object '%s'.\n", 19412262Sandreas.sandberg@arm.com obj_name); 19512262Sandreas.sandberg@arm.com kernelExtras.push_back(obj); 19612262Sandreas.sandberg@arm.com } 1978885SAli.Saidi@ARM.com } 1988885SAli.Saidi@ARM.com 19911838SCurtis.Dunham@arm.com // increment the number of running systems 2008885SAli.Saidi@ARM.com numSystemsRunning++; 2018885SAli.Saidi@ARM.com 2029053Sdam.sunwoo@arm.com // Set back pointers to the system in all memories 2039053Sdam.sunwoo@arm.com for (int x = 0; x < params()->memories.size(); x++) 2049053Sdam.sunwoo@arm.com params()->memories[x]->system(this); 2052SN/A} 2062SN/A 2072SN/ASystem::~System() 2082SN/A{ 2091070SN/A delete kernelSymtab; 2101070SN/A delete kernel; 2118666SPrakash.Ramrakhyani@arm.com 2128666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds; j++) 2138666SPrakash.Ramrakhyani@arm.com delete workItemStats[j]; 2142SN/A} 2152SN/A 2168706Sandreas.hansson@arm.comvoid 2178706Sandreas.hansson@arm.comSystem::init() 2188706Sandreas.hansson@arm.com{ 2198706Sandreas.hansson@arm.com // check that the system port is connected 2208706Sandreas.hansson@arm.com if (!_systemPort.isConnected()) 2218706Sandreas.hansson@arm.com panic("System port on %s is not connected.\n", name()); 2228706Sandreas.hansson@arm.com} 2238706Sandreas.hansson@arm.com 22413784Sgabeblack@google.comPort & 22513784Sgabeblack@google.comSystem::getPort(const std::string &if_name, PortID idx) 2268703Sandreas.hansson@arm.com{ 2278703Sandreas.hansson@arm.com // no need to distinguish at the moment (besides checking) 2288922Swilliam.wang@arm.com return _systemPort; 2298703Sandreas.hansson@arm.com} 2308703Sandreas.hansson@arm.com 2312901Ssaidi@eecs.umich.eduvoid 2324762Snate@binkert.orgSystem::setMemoryMode(Enums::MemoryMode mode) 2332901Ssaidi@eecs.umich.edu{ 23410913Sandreas.sandberg@arm.com assert(drainState() == DrainState::Drained); 2352901Ssaidi@eecs.umich.edu memoryMode = mode; 2362901Ssaidi@eecs.umich.edu} 2372901Ssaidi@eecs.umich.edu 2383960Sgblack@eecs.umich.edubool System::breakpoint() 2393960Sgblack@eecs.umich.edu{ 2404095Sbinkertn@umich.edu if (remoteGDB.size()) 2414095Sbinkertn@umich.edu return remoteGDB[0]->breakpoint(); 2424095Sbinkertn@umich.edu return false; 2433960Sgblack@eecs.umich.edu} 2443960Sgblack@eecs.umich.edu 24511005Sandreas.sandberg@arm.comContextID 24611005Sandreas.sandberg@arm.comSystem::registerThreadContext(ThreadContext *tc, ContextID assigned) 2472SN/A{ 24812443Sgabeblack@google.com int id = assigned; 24912443Sgabeblack@google.com if (id == InvalidContextID) { 25012443Sgabeblack@google.com // Find an unused context ID for this thread. 25112443Sgabeblack@google.com id = 0; 25212443Sgabeblack@google.com while (id < threadContexts.size() && threadContexts[id]) 25312443Sgabeblack@google.com id++; 2541806SN/A } 2551806SN/A 25612443Sgabeblack@google.com if (threadContexts.size() <= id) 25712443Sgabeblack@google.com threadContexts.resize(id + 1); 25812443Sgabeblack@google.com 25912443Sgabeblack@google.com fatal_if(threadContexts[id], 26012443Sgabeblack@google.com "Cannot have two CPUs with the same id (%d)\n", id); 2611806SN/A 2622680Sktlim@umich.edu threadContexts[id] = tc; 2631070SN/A 2649850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 2655512SMichael.Adler@intel.com int port = getRemoteGDBPort(); 2667445Ssteve.reinhardt@amd.com if (port) { 26712449Sgabeblack@google.com RemoteGDB *rgdb = new RemoteGDB(this, tc, port + id); 26812449Sgabeblack@google.com rgdb->listen(); 2697445Ssteve.reinhardt@amd.com 27012122Sjose.marinho@arm.com BaseCPU *cpu = tc->getCpuPtr(); 27112122Sjose.marinho@arm.com if (cpu->waitForRemoteGDB()) { 27212122Sjose.marinho@arm.com inform("%s: Waiting for a remote GDB connection on port %d.\n", 27312449Sgabeblack@google.com cpu->name(), rgdb->port()); 27412122Sjose.marinho@arm.com 27512449Sgabeblack@google.com rgdb->connect(); 27612122Sjose.marinho@arm.com } 2774095Sbinkertn@umich.edu if (remoteGDB.size() <= id) { 2784095Sbinkertn@umich.edu remoteGDB.resize(id + 1); 2794095Sbinkertn@umich.edu } 2804095Sbinkertn@umich.edu 2814095Sbinkertn@umich.edu remoteGDB[id] = rgdb; 2821070SN/A } 2839850Sandreas.hansson@arm.com#endif 2841070SN/A 2857914SBrad.Beckmann@amd.com activeCpus.push_back(false); 2867914SBrad.Beckmann@amd.com 2871806SN/A return id; 288180SN/A} 28975SN/A 2906029Ssteve.reinhardt@amd.comint 2916029Ssteve.reinhardt@amd.comSystem::numRunningContexts() 2926029Ssteve.reinhardt@amd.com{ 29312515Sgiacomo.travaglini@arm.com return std::count_if( 29412515Sgiacomo.travaglini@arm.com threadContexts.cbegin(), 29512515Sgiacomo.travaglini@arm.com threadContexts.cend(), 29612515Sgiacomo.travaglini@arm.com [] (ThreadContext* tc) { 29713644Sqtt2@cornell.edu return ((tc->status() != ThreadContext::Halted) && 29813644Sqtt2@cornell.edu (tc->status() != ThreadContext::Halting)); 29912515Sgiacomo.travaglini@arm.com } 30012515Sgiacomo.travaglini@arm.com ); 3016029Ssteve.reinhardt@amd.com} 3026029Ssteve.reinhardt@amd.com 303180SN/Avoid 3047733SAli.Saidi@ARM.comSystem::initState() 3051129SN/A{ 3068769Sgblack@eecs.umich.edu if (FullSystem) { 3079172Snilay@cs.wisc.edu for (int i = 0; i < threadContexts.size(); i++) 3088769Sgblack@eecs.umich.edu TheISA::startupCPU(threadContexts[i], i); 3098799Sgblack@eecs.umich.edu // Moved from the constructor to here since it relies on the 3108799Sgblack@eecs.umich.edu // address map being resolved in the interconnect 3118799Sgblack@eecs.umich.edu /** 3128799Sgblack@eecs.umich.edu * Load the kernel code into memory 3138799Sgblack@eecs.umich.edu */ 3148885SAli.Saidi@ARM.com if (params()->kernel != "") { 31510282Sdam.sunwoo@arm.com if (params()->kernel_addr_check) { 31610282Sdam.sunwoo@arm.com // Validate kernel mapping before loading binary 31710282Sdam.sunwoo@arm.com if (!(isMemAddr((kernelStart & loadAddrMask) + 31810282Sdam.sunwoo@arm.com loadAddrOffset) && 31910282Sdam.sunwoo@arm.com isMemAddr((kernelEnd & loadAddrMask) + 32010282Sdam.sunwoo@arm.com loadAddrOffset))) { 32110282Sdam.sunwoo@arm.com fatal("Kernel is mapped to invalid location (not memory). " 32210282Sdam.sunwoo@arm.com "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n", 32310282Sdam.sunwoo@arm.com kernelStart, 32410282Sdam.sunwoo@arm.com kernelEnd, (kernelStart & loadAddrMask) + 32510282Sdam.sunwoo@arm.com loadAddrOffset, 32610282Sdam.sunwoo@arm.com (kernelEnd & loadAddrMask) + loadAddrOffset); 32710282Sdam.sunwoo@arm.com } 3289187SKrishnendra.Nathella@arm.com } 3298799Sgblack@eecs.umich.edu // Load program sections into memory 33010037SARM gem5 Developers kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset); 33112262Sandreas.sandberg@arm.com for (const auto &extra_kernel : kernelExtras) { 33212262Sandreas.sandberg@arm.com extra_kernel->loadSections(physProxy, loadAddrMask, 33312262Sandreas.sandberg@arm.com loadAddrOffset); 33412262Sandreas.sandberg@arm.com } 3358706Sandreas.hansson@arm.com 3368799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel start = %#x\n", kernelStart); 3378799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel end = %#x\n", kernelEnd); 3388799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry); 3398799Sgblack@eecs.umich.edu DPRINTF(Loader, "Kernel loaded...\n"); 3408799Sgblack@eecs.umich.edu } 3418706Sandreas.hansson@arm.com } 3421129SN/A} 3431129SN/A 3441129SN/Avoid 34511005Sandreas.sandberg@arm.comSystem::replaceThreadContext(ThreadContext *tc, ContextID context_id) 346180SN/A{ 3475713Shsul@eecs.umich.edu if (context_id >= threadContexts.size()) { 3482680Sktlim@umich.edu panic("replaceThreadContext: bad id, %d >= %d\n", 3495713Shsul@eecs.umich.edu context_id, threadContexts.size()); 350180SN/A } 351180SN/A 3525713Shsul@eecs.umich.edu threadContexts[context_id] = tc; 3535713Shsul@eecs.umich.edu if (context_id < remoteGDB.size()) 3545713Shsul@eecs.umich.edu remoteGDB[context_id]->replaceThreadContext(tc); 3552SN/A} 3562SN/A 35712100SCurtis.Dunham@arm.combool 35812100SCurtis.Dunham@arm.comSystem::validKvmEnvironment() const 35912100SCurtis.Dunham@arm.com{ 36012100SCurtis.Dunham@arm.com#if USE_KVM 36112100SCurtis.Dunham@arm.com if (threadContexts.empty()) 36212100SCurtis.Dunham@arm.com return false; 36312100SCurtis.Dunham@arm.com 36412100SCurtis.Dunham@arm.com for (auto tc : threadContexts) { 36512100SCurtis.Dunham@arm.com if (dynamic_cast<BaseKvmCPU*>(tc->getCpuPtr()) == nullptr) { 36612100SCurtis.Dunham@arm.com return false; 36712100SCurtis.Dunham@arm.com } 36812100SCurtis.Dunham@arm.com } 36912100SCurtis.Dunham@arm.com return true; 37012100SCurtis.Dunham@arm.com#else 37112100SCurtis.Dunham@arm.com return false; 37212100SCurtis.Dunham@arm.com#endif 37312100SCurtis.Dunham@arm.com} 37412100SCurtis.Dunham@arm.com 3752378SN/AAddr 3768601Ssteve.reinhardt@amd.comSystem::allocPhysPages(int npages) 3772378SN/A{ 37810318Sandreas.hansson@arm.com Addr return_addr = pagePtr << PageShift; 3798601Ssteve.reinhardt@amd.com pagePtr += npages; 38010553Salexandru.dutu@amd.com 38110553Salexandru.dutu@amd.com Addr next_return_addr = pagePtr << PageShift; 38210553Salexandru.dutu@amd.com 38310553Salexandru.dutu@amd.com AddrRange m5opRange(0xffff0000, 0xffffffff); 38410553Salexandru.dutu@amd.com if (m5opRange.contains(next_return_addr)) { 38510553Salexandru.dutu@amd.com warn("Reached m5ops MMIO region\n"); 38610553Salexandru.dutu@amd.com return_addr = 0xffffffff; 38710553Salexandru.dutu@amd.com pagePtr = 0xffffffff >> PageShift; 38810553Salexandru.dutu@amd.com } 38910553Salexandru.dutu@amd.com 39010318Sandreas.hansson@arm.com if ((pagePtr << PageShift) > physmem.totalSize()) 3913162Ssaidi@eecs.umich.edu fatal("Out of memory, please increase size of physical memory."); 3922378SN/A return return_addr; 3932378SN/A} 3945795Ssaidi@eecs.umich.edu 3955795Ssaidi@eecs.umich.eduAddr 3968931Sandreas.hansson@arm.comSystem::memSize() const 3975795Ssaidi@eecs.umich.edu{ 3988931Sandreas.hansson@arm.com return physmem.totalSize(); 3995795Ssaidi@eecs.umich.edu} 4005795Ssaidi@eecs.umich.edu 4015795Ssaidi@eecs.umich.eduAddr 4028931Sandreas.hansson@arm.comSystem::freeMemSize() const 4035795Ssaidi@eecs.umich.edu{ 40410318Sandreas.hansson@arm.com return physmem.totalSize() - (pagePtr << PageShift); 4055795Ssaidi@eecs.umich.edu} 4065795Ssaidi@eecs.umich.edu 4078460SAli.Saidi@ARM.combool 4088931Sandreas.hansson@arm.comSystem::isMemAddr(Addr addr) const 4098460SAli.Saidi@ARM.com{ 4108931Sandreas.hansson@arm.com return physmem.isMemAddr(addr); 4118460SAli.Saidi@ARM.com} 4128460SAli.Saidi@ARM.com 4131070SN/Avoid 4149342SAndreas.Sandberg@arm.comSystem::drainResume() 4157897Shestness@cs.utexas.edu{ 4167897Shestness@cs.utexas.edu totalNumInsts = 0; 4177897Shestness@cs.utexas.edu} 4187897Shestness@cs.utexas.edu 4197897Shestness@cs.utexas.eduvoid 42010905Sandreas.sandberg@arm.comSystem::serialize(CheckpointOut &cp) const 4211070SN/A{ 4228769Sgblack@eecs.umich.edu if (FullSystem) 42310905Sandreas.sandberg@arm.com kernelSymtab->serialize("kernel_symtab", cp); 4247770SAli.Saidi@ARM.com SERIALIZE_SCALAR(pagePtr); 42510905Sandreas.sandberg@arm.com serializeSymtab(cp); 4269293Sandreas.hansson@arm.com 4279293Sandreas.hansson@arm.com // also serialize the memories in the system 42810905Sandreas.sandberg@arm.com physmem.serializeSection(cp, "physmem"); 4291070SN/A} 4301070SN/A 4311070SN/A 4321070SN/Avoid 43310905Sandreas.sandberg@arm.comSystem::unserialize(CheckpointIn &cp) 4341070SN/A{ 4358769Sgblack@eecs.umich.edu if (FullSystem) 43610905Sandreas.sandberg@arm.com kernelSymtab->unserialize("kernel_symtab", cp); 4377770SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(pagePtr); 43810905Sandreas.sandberg@arm.com unserializeSymtab(cp); 4399293Sandreas.hansson@arm.com 4409293Sandreas.hansson@arm.com // also unserialize the memories in the system 44110905Sandreas.sandberg@arm.com physmem.unserializeSection(cp, "physmem"); 4421070SN/A} 4432SN/A 4442SN/Avoid 4458666SPrakash.Ramrakhyani@arm.comSystem::regStats() 4468666SPrakash.Ramrakhyani@arm.com{ 44713892Sgabeblack@google.com SimObject::regStats(); 44811522Sstephan.diestelhorst@arm.com 4498666SPrakash.Ramrakhyani@arm.com for (uint32_t j = 0; j < numWorkIds ; j++) { 4508666SPrakash.Ramrakhyani@arm.com workItemStats[j] = new Stats::Histogram(); 4518666SPrakash.Ramrakhyani@arm.com stringstream namestr; 4528666SPrakash.Ramrakhyani@arm.com ccprintf(namestr, "work_item_type%d", j); 4538666SPrakash.Ramrakhyani@arm.com workItemStats[j]->init(20) 4548666SPrakash.Ramrakhyani@arm.com .name(name() + "." + namestr.str()) 4558666SPrakash.Ramrakhyani@arm.com .desc("Run time stat for" + namestr.str()) 4568666SPrakash.Ramrakhyani@arm.com .prereq(*workItemStats[j]); 4578666SPrakash.Ramrakhyani@arm.com } 4588666SPrakash.Ramrakhyani@arm.com} 4598666SPrakash.Ramrakhyani@arm.com 4608666SPrakash.Ramrakhyani@arm.comvoid 4618666SPrakash.Ramrakhyani@arm.comSystem::workItemEnd(uint32_t tid, uint32_t workid) 4628666SPrakash.Ramrakhyani@arm.com{ 4638666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 4648666SPrakash.Ramrakhyani@arm.com if (!lastWorkItemStarted.count(p)) 4658666SPrakash.Ramrakhyani@arm.com return; 4668666SPrakash.Ramrakhyani@arm.com 4678666SPrakash.Ramrakhyani@arm.com Tick samp = curTick() - lastWorkItemStarted[p]; 4688666SPrakash.Ramrakhyani@arm.com DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp); 4698666SPrakash.Ramrakhyani@arm.com 4708666SPrakash.Ramrakhyani@arm.com if (workid >= numWorkIds) 4718666SPrakash.Ramrakhyani@arm.com fatal("Got workid greater than specified in system configuration\n"); 4728666SPrakash.Ramrakhyani@arm.com 4738666SPrakash.Ramrakhyani@arm.com workItemStats[workid]->sample(samp); 4748666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted.erase(p); 4758666SPrakash.Ramrakhyani@arm.com} 4768666SPrakash.Ramrakhyani@arm.com 4778666SPrakash.Ramrakhyani@arm.comvoid 4782SN/ASystem::printSystems() 4792SN/A{ 48010375Sandreas.hansson@arm.com ios::fmtflags flags(cerr.flags()); 48110375Sandreas.hansson@arm.com 4822SN/A vector<System *>::iterator i = systemList.begin(); 4832SN/A vector<System *>::iterator end = systemList.end(); 4842SN/A for (; i != end; ++i) { 4852SN/A System *sys = *i; 4862SN/A cerr << "System " << sys->name() << ": " << hex << sys << endl; 4872SN/A } 48810375Sandreas.hansson@arm.com 48910375Sandreas.hansson@arm.com cerr.flags(flags); 4902SN/A} 4912SN/A 4922SN/Avoid 4932SN/AprintSystems() 4942SN/A{ 4952SN/A System::printSystems(); 4962SN/A} 4972SN/A 49812965Sgiacomo.travaglini@arm.comstd::string 49912965Sgiacomo.travaglini@arm.comSystem::stripSystemName(const std::string& master_name) const 50012965Sgiacomo.travaglini@arm.com{ 50112965Sgiacomo.travaglini@arm.com if (startswith(master_name, name())) { 50212965Sgiacomo.travaglini@arm.com return master_name.substr(name().size()); 50312965Sgiacomo.travaglini@arm.com } else { 50412965Sgiacomo.travaglini@arm.com return master_name; 50512965Sgiacomo.travaglini@arm.com } 50612965Sgiacomo.travaglini@arm.com} 50712965Sgiacomo.travaglini@arm.com 5088832SAli.Saidi@ARM.comMasterID 50912965Sgiacomo.travaglini@arm.comSystem::lookupMasterId(const SimObject* obj) const 51012965Sgiacomo.travaglini@arm.com{ 51112965Sgiacomo.travaglini@arm.com MasterID id = Request::invldMasterId; 51212965Sgiacomo.travaglini@arm.com 51312965Sgiacomo.travaglini@arm.com // number of occurrences of the SimObject pointer 51412965Sgiacomo.travaglini@arm.com // in the master list. 51512965Sgiacomo.travaglini@arm.com auto obj_number = 0; 51612965Sgiacomo.travaglini@arm.com 51712965Sgiacomo.travaglini@arm.com for (int i = 0; i < masters.size(); i++) { 51812965Sgiacomo.travaglini@arm.com if (masters[i].obj == obj) { 51912965Sgiacomo.travaglini@arm.com id = i; 52012965Sgiacomo.travaglini@arm.com obj_number++; 52112965Sgiacomo.travaglini@arm.com } 52212965Sgiacomo.travaglini@arm.com } 52312965Sgiacomo.travaglini@arm.com 52412965Sgiacomo.travaglini@arm.com fatal_if(obj_number > 1, 52512965Sgiacomo.travaglini@arm.com "Cannot lookup MasterID by SimObject pointer: " 52612965Sgiacomo.travaglini@arm.com "More than one master is sharing the same SimObject\n"); 52712965Sgiacomo.travaglini@arm.com 52812965Sgiacomo.travaglini@arm.com return id; 52912965Sgiacomo.travaglini@arm.com} 53012965Sgiacomo.travaglini@arm.com 53112965Sgiacomo.travaglini@arm.comMasterID 53212965Sgiacomo.travaglini@arm.comSystem::lookupMasterId(const std::string& master_name) const 53312965Sgiacomo.travaglini@arm.com{ 53412965Sgiacomo.travaglini@arm.com std::string name = stripSystemName(master_name); 53512965Sgiacomo.travaglini@arm.com 53612965Sgiacomo.travaglini@arm.com for (int i = 0; i < masters.size(); i++) { 53712965Sgiacomo.travaglini@arm.com if (masters[i].masterName == name) { 53812965Sgiacomo.travaglini@arm.com return i; 53912965Sgiacomo.travaglini@arm.com } 54012965Sgiacomo.travaglini@arm.com } 54112965Sgiacomo.travaglini@arm.com 54212965Sgiacomo.travaglini@arm.com return Request::invldMasterId; 54312965Sgiacomo.travaglini@arm.com} 54412965Sgiacomo.travaglini@arm.com 54512965Sgiacomo.travaglini@arm.comMasterID 54612965Sgiacomo.travaglini@arm.comSystem::getGlobalMasterId(const std::string& master_name) 5478832SAli.Saidi@ARM.com{ 54812680Sgiacomo.travaglini@arm.com return _getMasterId(nullptr, master_name); 54912680Sgiacomo.travaglini@arm.com} 55012680Sgiacomo.travaglini@arm.com 55112680Sgiacomo.travaglini@arm.comMasterID 55212680Sgiacomo.travaglini@arm.comSystem::getMasterId(const SimObject* master, std::string submaster) 55312680Sgiacomo.travaglini@arm.com{ 55412680Sgiacomo.travaglini@arm.com auto master_name = leafMasterName(master, submaster); 55512680Sgiacomo.travaglini@arm.com return _getMasterId(master, master_name); 55612680Sgiacomo.travaglini@arm.com} 55712680Sgiacomo.travaglini@arm.com 55812680Sgiacomo.travaglini@arm.comMasterID 55912965Sgiacomo.travaglini@arm.comSystem::_getMasterId(const SimObject* master, const std::string& master_name) 56012680Sgiacomo.travaglini@arm.com{ 56112965Sgiacomo.travaglini@arm.com std::string name = stripSystemName(master_name); 5628832SAli.Saidi@ARM.com 5638832SAli.Saidi@ARM.com // CPUs in switch_cpus ask for ids again after switching 56412680Sgiacomo.travaglini@arm.com for (int i = 0; i < masters.size(); i++) { 56512965Sgiacomo.travaglini@arm.com if (masters[i].masterName == name) { 5668832SAli.Saidi@ARM.com return i; 5678832SAli.Saidi@ARM.com } 5688832SAli.Saidi@ARM.com } 5698832SAli.Saidi@ARM.com 5708986SAli.Saidi@ARM.com // Verify that the statistics haven't been enabled yet 5718986SAli.Saidi@ARM.com // Otherwise objects will have sized their stat buckets and 5728986SAli.Saidi@ARM.com // they will be too small 5738832SAli.Saidi@ARM.com 57410367SAndrew.Bardsley@arm.com if (Stats::enabled()) { 57510367SAndrew.Bardsley@arm.com fatal("Can't request a masterId after regStats(). " 57610367SAndrew.Bardsley@arm.com "You must do so in init().\n"); 57710367SAndrew.Bardsley@arm.com } 5788832SAli.Saidi@ARM.com 57912680Sgiacomo.travaglini@arm.com // Generate a new MasterID incrementally 58012680Sgiacomo.travaglini@arm.com MasterID master_id = masters.size(); 5818832SAli.Saidi@ARM.com 58212680Sgiacomo.travaglini@arm.com // Append the new Master metadata to the group of system Masters. 58312965Sgiacomo.travaglini@arm.com masters.emplace_back(master, name, master_id); 58412680Sgiacomo.travaglini@arm.com 58512680Sgiacomo.travaglini@arm.com return masters.back().masterId; 58612680Sgiacomo.travaglini@arm.com} 58712680Sgiacomo.travaglini@arm.com 58812680Sgiacomo.travaglini@arm.comstd::string 58912680Sgiacomo.travaglini@arm.comSystem::leafMasterName(const SimObject* master, const std::string& submaster) 59012680Sgiacomo.travaglini@arm.com{ 59112694Sgiacomo.travaglini@arm.com if (submaster.empty()) { 59212694Sgiacomo.travaglini@arm.com return master->name(); 59312694Sgiacomo.travaglini@arm.com } else { 59412694Sgiacomo.travaglini@arm.com // Get the full master name by appending the submaster name to 59512694Sgiacomo.travaglini@arm.com // the root SimObject master name 59612694Sgiacomo.travaglini@arm.com return master->name() + "." + submaster; 59712694Sgiacomo.travaglini@arm.com } 5988832SAli.Saidi@ARM.com} 5998832SAli.Saidi@ARM.com 6008832SAli.Saidi@ARM.comstd::string 6018832SAli.Saidi@ARM.comSystem::getMasterName(MasterID master_id) 6028832SAli.Saidi@ARM.com{ 60312680Sgiacomo.travaglini@arm.com if (master_id >= masters.size()) 6048832SAli.Saidi@ARM.com fatal("Invalid master_id passed to getMasterName()\n"); 6058832SAli.Saidi@ARM.com 60612680Sgiacomo.travaglini@arm.com const auto& master_info = masters[master_id]; 60712680Sgiacomo.travaglini@arm.com return master_info.masterName; 6088832SAli.Saidi@ARM.com} 6098832SAli.Saidi@ARM.com 6104762Snate@binkert.orgSystem * 6114762Snate@binkert.orgSystemParams::create() 6122424SN/A{ 6135530Snate@binkert.org return new System(this); 6142424SN/A} 615