1/*
2 * Copyright (c) 2011-2014,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2006 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 *          Lisa Hsu
43 *          Nathan Binkert
44 *          Ali Saidi
45 *          Rick Strong
46 */
47
48#include "sim/system.hh"
49
50#include <algorithm>
51
52#include "arch/remote_gdb.hh"
53#include "arch/utility.hh"
54#include "base/loader/object_file.hh"
55#include "base/loader/symtab.hh"
56#include "base/str.hh"
57#include "base/trace.hh"
58#include "config/use_kvm.hh"
59#if USE_KVM
60#include "cpu/kvm/base.hh"
61#include "cpu/kvm/vm.hh"
62#endif
63#include "cpu/base.hh"
64#include "cpu/thread_context.hh"
65#include "debug/Loader.hh"
66#include "debug/WorkItems.hh"
67#include "mem/abstract_mem.hh"
68#include "mem/physical.hh"
69#include "params/System.hh"
70#include "sim/byteswap.hh"
71#include "sim/debug.hh"
72#include "sim/full_system.hh"
73#include "sim/redirect_path.hh"
74
75/**
76 * To avoid linking errors with LTO, only include the header if we
77 * actually have a definition.
78 */
79#if THE_ISA != NULL_ISA
80#include "kern/kernel_stats.hh"
81
82#endif
83
84using namespace std;
85using namespace TheISA;
86
87vector<System *> System::systemList;
88
89int System::numSystemsRunning = 0;
90
91System::System(Params *p)
92    : SimObject(p), _systemPort("system_port", this),
93      multiThread(p->multi_thread),
94      pagePtr(0),
95      init_param(p->init_param),
96      physProxy(_systemPort, p->cache_line_size),
97      kernelSymtab(nullptr),
98      kernel(nullptr),
99      loadAddrMask(p->load_addr_mask),
100      loadAddrOffset(p->load_offset),
101#if USE_KVM
102      kvmVM(p->kvm_vm),
103#else
104      kvmVM(nullptr),
105#endif
106      physmem(name() + ".physmem", p->memories, p->mmap_using_noreserve),
107      memoryMode(p->mem_mode),
108      _cacheLineSize(p->cache_line_size),
109      workItemsBegin(0),
110      workItemsEnd(0),
111      numWorkIds(p->num_work_ids),
112      thermalModel(p->thermal_model),
113      _params(p),
114      totalNumInsts(0),
115      instEventQueue("system instruction-based event queue"),
116      redirectPaths(p->redirect_paths)
117{
118
119    // add self to global system list
120    systemList.push_back(this);
121
122#if USE_KVM
123    if (kvmVM) {
124        kvmVM->setSystem(this);
125    }
126#endif
127
128    if (FullSystem) {
129        kernelSymtab = new SymbolTable;
130        if (!debugSymbolTable)
131            debugSymbolTable = new SymbolTable;
132    }
133
134    // check if the cache line size is a value known to work
135    if (!(_cacheLineSize == 16 || _cacheLineSize == 32 ||
136          _cacheLineSize == 64 || _cacheLineSize == 128))
137        warn_once("Cache line size is neither 16, 32, 64 nor 128 bytes.\n");
138
139    // Get the generic system master IDs
140    MasterID tmp_id M5_VAR_USED;
141    tmp_id = getMasterId(this, "writebacks");
142    assert(tmp_id == Request::wbMasterId);
143    tmp_id = getMasterId(this, "functional");
144    assert(tmp_id == Request::funcMasterId);
145    tmp_id = getMasterId(this, "interrupt");
146    assert(tmp_id == Request::intMasterId);
147
148    if (FullSystem) {
149        if (params()->kernel == "") {
150            inform("No kernel set for full system simulation. "
151                   "Assuming you know what you're doing\n");
152        } else {
153            // Get the kernel code
154            kernel = createObjectFile(params()->kernel);
155            inform("kernel located at: %s", params()->kernel);
156
157            if (kernel == NULL)
158                fatal("Could not load kernel file %s", params()->kernel);
159
160            // setup entry points
161            kernelStart = kernel->textBase();
162            kernelEnd = kernel->bssBase() + kernel->bssSize();
163            kernelEntry = kernel->entryPoint();
164
165            // If load_addr_mask is set to 0x0, then auto-calculate
166            // the smallest mask to cover all kernel addresses so gem5
167            // can relocate the kernel to a new offset.
168            if (loadAddrMask == 0) {
169                Addr shift_amt = findMsbSet(kernelEnd - kernelStart) + 1;
170                loadAddrMask = ((Addr)1 << shift_amt) - 1;
171            }
172
173            // load symbols
174            if (!kernel->loadGlobalSymbols(kernelSymtab))
175                fatal("could not load kernel symbols\n");
176
177            if (!kernel->loadLocalSymbols(kernelSymtab))
178                fatal("could not load kernel local symbols\n");
179
180            if (!kernel->loadGlobalSymbols(debugSymbolTable))
181                fatal("could not load kernel symbols\n");
182
183            if (!kernel->loadLocalSymbols(debugSymbolTable))
184                fatal("could not load kernel local symbols\n");
185
186            // Loading only needs to happen once and after memory system is
187            // connected so it will happen in initState()
188        }
189
190        for (const auto &obj_name : p->kernel_extras) {
191            inform("Loading additional kernel object: %s", obj_name);
192            ObjectFile *obj = createObjectFile(obj_name);
193            fatal_if(!obj, "Failed to additional kernel object '%s'.\n",
194                     obj_name);
195            kernelExtras.push_back(obj);
196        }
197    }
198
199    // increment the number of running systems
200    numSystemsRunning++;
201
202    // Set back pointers to the system in all memories
203    for (int x = 0; x < params()->memories.size(); x++)
204        params()->memories[x]->system(this);
205}
206
207System::~System()
208{
209    delete kernelSymtab;
210    delete kernel;
211
212    for (uint32_t j = 0; j < numWorkIds; j++)
213        delete workItemStats[j];
214}
215
216void
217System::init()
218{
219    // check that the system port is connected
220    if (!_systemPort.isConnected())
221        panic("System port on %s is not connected.\n", name());
222}
223
224Port &
225System::getPort(const std::string &if_name, PortID idx)
226{
227    // no need to distinguish at the moment (besides checking)
228    return _systemPort;
229}
230
231void
232System::setMemoryMode(Enums::MemoryMode mode)
233{
234    assert(drainState() == DrainState::Drained);
235    memoryMode = mode;
236}
237
238bool System::breakpoint()
239{
240    if (remoteGDB.size())
241        return remoteGDB[0]->breakpoint();
242    return false;
243}
244
245ContextID
246System::registerThreadContext(ThreadContext *tc, ContextID assigned)
247{
248    int id = assigned;
249    if (id == InvalidContextID) {
250        // Find an unused context ID for this thread.
251        id = 0;
252        while (id < threadContexts.size() && threadContexts[id])
253            id++;
254    }
255
256    if (threadContexts.size() <= id)
257        threadContexts.resize(id + 1);
258
259    fatal_if(threadContexts[id],
260             "Cannot have two CPUs with the same id (%d)\n", id);
261
262    threadContexts[id] = tc;
263
264#if THE_ISA != NULL_ISA
265    int port = getRemoteGDBPort();
266    if (port) {
267        RemoteGDB *rgdb = new RemoteGDB(this, tc, port + id);
268        rgdb->listen();
269
270        BaseCPU *cpu = tc->getCpuPtr();
271        if (cpu->waitForRemoteGDB()) {
272            inform("%s: Waiting for a remote GDB connection on port %d.\n",
273                   cpu->name(), rgdb->port());
274
275            rgdb->connect();
276        }
277        if (remoteGDB.size() <= id) {
278            remoteGDB.resize(id + 1);
279        }
280
281        remoteGDB[id] = rgdb;
282    }
283#endif
284
285    activeCpus.push_back(false);
286
287    return id;
288}
289
290int
291System::numRunningContexts()
292{
293    return std::count_if(
294        threadContexts.cbegin(),
295        threadContexts.cend(),
296        [] (ThreadContext* tc) {
297            return ((tc->status() != ThreadContext::Halted) &&
298                    (tc->status() != ThreadContext::Halting));
299        }
300    );
301}
302
303void
304System::initState()
305{
306    if (FullSystem) {
307        for (int i = 0; i < threadContexts.size(); i++)
308            TheISA::startupCPU(threadContexts[i], i);
309        // Moved from the constructor to here since it relies on the
310        // address map being resolved in the interconnect
311        /**
312         * Load the kernel code into memory
313         */
314        if (params()->kernel != "")  {
315            if (params()->kernel_addr_check) {
316                // Validate kernel mapping before loading binary
317                if (!(isMemAddr((kernelStart & loadAddrMask) +
318                                loadAddrOffset) &&
319                      isMemAddr((kernelEnd & loadAddrMask) +
320                                loadAddrOffset))) {
321                    fatal("Kernel is mapped to invalid location (not memory). "
322                          "kernelStart 0x(%x) - kernelEnd 0x(%x) %#x:%#x\n",
323                          kernelStart,
324                          kernelEnd, (kernelStart & loadAddrMask) +
325                          loadAddrOffset,
326                          (kernelEnd & loadAddrMask) + loadAddrOffset);
327                }
328            }
329            // Load program sections into memory
330            kernel->loadSections(physProxy, loadAddrMask, loadAddrOffset);
331            for (const auto &extra_kernel : kernelExtras) {
332                extra_kernel->loadSections(physProxy, loadAddrMask,
333                                           loadAddrOffset);
334            }
335
336            DPRINTF(Loader, "Kernel start = %#x\n", kernelStart);
337            DPRINTF(Loader, "Kernel end   = %#x\n", kernelEnd);
338            DPRINTF(Loader, "Kernel entry = %#x\n", kernelEntry);
339            DPRINTF(Loader, "Kernel loaded...\n");
340        }
341    }
342}
343
344void
345System::replaceThreadContext(ThreadContext *tc, ContextID context_id)
346{
347    if (context_id >= threadContexts.size()) {
348        panic("replaceThreadContext: bad id, %d >= %d\n",
349              context_id, threadContexts.size());
350    }
351
352    threadContexts[context_id] = tc;
353    if (context_id < remoteGDB.size())
354        remoteGDB[context_id]->replaceThreadContext(tc);
355}
356
357bool
358System::validKvmEnvironment() const
359{
360#if USE_KVM
361    if (threadContexts.empty())
362        return false;
363
364    for (auto tc : threadContexts) {
365        if (dynamic_cast<BaseKvmCPU*>(tc->getCpuPtr()) == nullptr) {
366            return false;
367        }
368    }
369    return true;
370#else
371    return false;
372#endif
373}
374
375Addr
376System::allocPhysPages(int npages)
377{
378    Addr return_addr = pagePtr << PageShift;
379    pagePtr += npages;
380
381    Addr next_return_addr = pagePtr << PageShift;
382
383    AddrRange m5opRange(0xffff0000, 0xffffffff);
384    if (m5opRange.contains(next_return_addr)) {
385        warn("Reached m5ops MMIO region\n");
386        return_addr = 0xffffffff;
387        pagePtr = 0xffffffff >> PageShift;
388    }
389
390    if ((pagePtr << PageShift) > physmem.totalSize())
391        fatal("Out of memory, please increase size of physical memory.");
392    return return_addr;
393}
394
395Addr
396System::memSize() const
397{
398    return physmem.totalSize();
399}
400
401Addr
402System::freeMemSize() const
403{
404   return physmem.totalSize() - (pagePtr << PageShift);
405}
406
407bool
408System::isMemAddr(Addr addr) const
409{
410    return physmem.isMemAddr(addr);
411}
412
413void
414System::drainResume()
415{
416    totalNumInsts = 0;
417}
418
419void
420System::serialize(CheckpointOut &cp) const
421{
422    if (FullSystem)
423        kernelSymtab->serialize("kernel_symtab", cp);
424    SERIALIZE_SCALAR(pagePtr);
425    serializeSymtab(cp);
426
427    // also serialize the memories in the system
428    physmem.serializeSection(cp, "physmem");
429}
430
431
432void
433System::unserialize(CheckpointIn &cp)
434{
435    if (FullSystem)
436        kernelSymtab->unserialize("kernel_symtab", cp);
437    UNSERIALIZE_SCALAR(pagePtr);
438    unserializeSymtab(cp);
439
440    // also unserialize the memories in the system
441    physmem.unserializeSection(cp, "physmem");
442}
443
444void
445System::regStats()
446{
447    SimObject::regStats();
448
449    for (uint32_t j = 0; j < numWorkIds ; j++) {
450        workItemStats[j] = new Stats::Histogram();
451        stringstream namestr;
452        ccprintf(namestr, "work_item_type%d", j);
453        workItemStats[j]->init(20)
454                         .name(name() + "." + namestr.str())
455                         .desc("Run time stat for" + namestr.str())
456                         .prereq(*workItemStats[j]);
457    }
458}
459
460void
461System::workItemEnd(uint32_t tid, uint32_t workid)
462{
463    std::pair<uint32_t,uint32_t> p(tid, workid);
464    if (!lastWorkItemStarted.count(p))
465        return;
466
467    Tick samp = curTick() - lastWorkItemStarted[p];
468    DPRINTF(WorkItems, "Work item end: %d\t%d\t%lld\n", tid, workid, samp);
469
470    if (workid >= numWorkIds)
471        fatal("Got workid greater than specified in system configuration\n");
472
473    workItemStats[workid]->sample(samp);
474    lastWorkItemStarted.erase(p);
475}
476
477void
478System::printSystems()
479{
480    ios::fmtflags flags(cerr.flags());
481
482    vector<System *>::iterator i = systemList.begin();
483    vector<System *>::iterator end = systemList.end();
484    for (; i != end; ++i) {
485        System *sys = *i;
486        cerr << "System " << sys->name() << ": " << hex << sys << endl;
487    }
488
489    cerr.flags(flags);
490}
491
492void
493printSystems()
494{
495    System::printSystems();
496}
497
498std::string
499System::stripSystemName(const std::string& master_name) const
500{
501    if (startswith(master_name, name())) {
502        return master_name.substr(name().size());
503    } else {
504        return master_name;
505    }
506}
507
508MasterID
509System::lookupMasterId(const SimObject* obj) const
510{
511    MasterID id = Request::invldMasterId;
512
513    // number of occurrences of the SimObject pointer
514    // in the master list.
515    auto obj_number = 0;
516
517    for (int i = 0; i < masters.size(); i++) {
518        if (masters[i].obj == obj) {
519            id = i;
520            obj_number++;
521        }
522    }
523
524    fatal_if(obj_number > 1,
525        "Cannot lookup MasterID by SimObject pointer: "
526        "More than one master is sharing the same SimObject\n");
527
528    return id;
529}
530
531MasterID
532System::lookupMasterId(const std::string& master_name) const
533{
534    std::string name = stripSystemName(master_name);
535
536    for (int i = 0; i < masters.size(); i++) {
537        if (masters[i].masterName == name) {
538            return i;
539        }
540    }
541
542    return Request::invldMasterId;
543}
544
545MasterID
546System::getGlobalMasterId(const std::string& master_name)
547{
548    return _getMasterId(nullptr, master_name);
549}
550
551MasterID
552System::getMasterId(const SimObject* master, std::string submaster)
553{
554    auto master_name = leafMasterName(master, submaster);
555    return _getMasterId(master, master_name);
556}
557
558MasterID
559System::_getMasterId(const SimObject* master, const std::string& master_name)
560{
561    std::string name = stripSystemName(master_name);
562
563    // CPUs in switch_cpus ask for ids again after switching
564    for (int i = 0; i < masters.size(); i++) {
565        if (masters[i].masterName == name) {
566            return i;
567        }
568    }
569
570    // Verify that the statistics haven't been enabled yet
571    // Otherwise objects will have sized their stat buckets and
572    // they will be too small
573
574    if (Stats::enabled()) {
575        fatal("Can't request a masterId after regStats(). "
576                "You must do so in init().\n");
577    }
578
579    // Generate a new MasterID incrementally
580    MasterID master_id = masters.size();
581
582    // Append the new Master metadata to the group of system Masters.
583    masters.emplace_back(master, name, master_id);
584
585    return masters.back().masterId;
586}
587
588std::string
589System::leafMasterName(const SimObject* master, const std::string& submaster)
590{
591    if (submaster.empty()) {
592        return master->name();
593    } else {
594        // Get the full master name by appending the submaster name to
595        // the root SimObject master name
596        return master->name() + "." + submaster;
597    }
598}
599
600std::string
601System::getMasterName(MasterID master_id)
602{
603    if (master_id >= masters.size())
604        fatal("Invalid master_id passed to getMasterName()\n");
605
606    const auto& master_info = masters[master_id];
607    return master_info.masterName;
608}
609
610System *
611SystemParams::create()
612{
613    return new System(this);
614}
615