12SN/A/* 212680Sgiacomo.travaglini@arm.com * Copyright (c) 2012, 2014, 2018 ARM Limited 38703Sandreas.hansson@arm.com * All rights reserved 48703Sandreas.hansson@arm.com * 58703Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68703Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78703Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88703Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98703Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108703Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118703Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128703Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138703Sandreas.hansson@arm.com * 141762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 157897Shestness@cs.utexas.edu * Copyright (c) 2011 Regents of the University of California 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 422665Ssaidi@eecs.umich.edu * Lisa Hsu 432665Ssaidi@eecs.umich.edu * Nathan Binkert 447897Shestness@cs.utexas.edu * Rick Strong 452SN/A */ 462SN/A 472SN/A#ifndef __SYSTEM_HH__ 482SN/A#define __SYSTEM_HH__ 492SN/A 502SN/A#include <string> 5111911SBrandon.Potter@amd.com#include <unordered_map> 529645SAndreas.Sandberg@ARM.com#include <utility> 5375SN/A#include <vector> 542SN/A 5510466Sandreas.hansson@arm.com#include "arch/isa_traits.hh" 562439SN/A#include "base/loader/symtab.hh" 57603SN/A#include "base/statistics.hh" 5810466Sandreas.hansson@arm.com#include "config/the_isa.hh" 594762Snate@binkert.org#include "enums/MemoryMode.hh" 6012680Sgiacomo.travaglini@arm.com#include "mem/mem_master.hh" 6111911SBrandon.Potter@amd.com#include "mem/physical.hh" 622520SN/A#include "mem/port.hh" 639847Sandreas.hansson@arm.com#include "mem/port_proxy.hh" 644762Snate@binkert.org#include "params/System.hh" 6511911SBrandon.Potter@amd.com#include "sim/futex_map.hh" 6613883Sdavid.hashe@amd.com#include "sim/redirect_path.hh" 6711909SBrandon.Potter@amd.com#include "sim/se_signal.hh" 6813892Sgabeblack@google.com#include "sim/sim_object.hh" 696658Snate@binkert.org 7010494Sandreas.hansson@arm.com/** 7110494Sandreas.hansson@arm.com * To avoid linking errors with LTO, only include the header if we 7210494Sandreas.hansson@arm.com * actually have the definition. 7310494Sandreas.hansson@arm.com */ 7410494Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 7510494Sandreas.hansson@arm.com#include "cpu/pc_event.hh" 7611911SBrandon.Potter@amd.com 7710494Sandreas.hansson@arm.com#endif 7810494Sandreas.hansson@arm.com 798769Sgblack@eecs.umich.educlass BaseRemoteGDB; 8011839SCurtis.Dunham@arm.comclass KvmVM; 811634SN/Aclass ObjectFile; 828769Sgblack@eecs.umich.educlass ThreadContext; 832SN/A 8413892Sgabeblack@google.comclass System : public SimObject 852SN/A{ 868703Sandreas.hansson@arm.com private: 878703Sandreas.hansson@arm.com 888703Sandreas.hansson@arm.com /** 898703Sandreas.hansson@arm.com * Private class for the system port which is only used as a 908703Sandreas.hansson@arm.com * master for debug access and for non-structural entities that do 918703Sandreas.hansson@arm.com * not have a port of their own. 928703Sandreas.hansson@arm.com */ 938922Swilliam.wang@arm.com class SystemPort : public MasterPort 948703Sandreas.hansson@arm.com { 958703Sandreas.hansson@arm.com public: 968703Sandreas.hansson@arm.com 978703Sandreas.hansson@arm.com /** 988703Sandreas.hansson@arm.com * Create a system port with a name and an owner. 998703Sandreas.hansson@arm.com */ 10013892Sgabeblack@google.com SystemPort(const std::string &_name, SimObject *_owner) 1018922Swilliam.wang@arm.com : MasterPort(_name, _owner) 1028703Sandreas.hansson@arm.com { } 10311169Sandreas.hansson@arm.com bool recvTimingResp(PacketPtr pkt) override 1048703Sandreas.hansson@arm.com { panic("SystemPort does not receive timing!\n"); return false; } 10511169Sandreas.hansson@arm.com void recvReqRetry() override 1068922Swilliam.wang@arm.com { panic("SystemPort does not expect retry!\n"); } 1078703Sandreas.hansson@arm.com }; 1088703Sandreas.hansson@arm.com 1098703Sandreas.hansson@arm.com SystemPort _systemPort; 1108703Sandreas.hansson@arm.com 111603SN/A public: 1122901Ssaidi@eecs.umich.edu 1138703Sandreas.hansson@arm.com /** 1148706Sandreas.hansson@arm.com * After all objects have been created and all ports are 1158706Sandreas.hansson@arm.com * connected, check that the system port is connected. 1168706Sandreas.hansson@arm.com */ 11711169Sandreas.hansson@arm.com void init() override; 1188706Sandreas.hansson@arm.com 1198706Sandreas.hansson@arm.com /** 1208852Sandreas.hansson@arm.com * Get a reference to the system port that can be used by 1218703Sandreas.hansson@arm.com * non-structural simulation objects like processes or threads, or 1228703Sandreas.hansson@arm.com * external entities like loaders and debuggers, etc, to access 1238703Sandreas.hansson@arm.com * the memory system. 1248703Sandreas.hansson@arm.com * 1258852Sandreas.hansson@arm.com * @return a reference to the system port we own 1268703Sandreas.hansson@arm.com */ 1278922Swilliam.wang@arm.com MasterPort& getSystemPort() { return _systemPort; } 1288703Sandreas.hansson@arm.com 1298703Sandreas.hansson@arm.com /** 1308703Sandreas.hansson@arm.com * Additional function to return the Port of a memory object. 1318703Sandreas.hansson@arm.com */ 13213784Sgabeblack@google.com Port &getPort(const std::string &if_name, 13313784Sgabeblack@google.com PortID idx=InvalidPortID) override; 1348703Sandreas.hansson@arm.com 1359524SAndreas.Sandberg@ARM.com /** @{ */ 1369524SAndreas.Sandberg@ARM.com /** 1379524SAndreas.Sandberg@ARM.com * Is the system in atomic mode? 1389524SAndreas.Sandberg@ARM.com * 1399524SAndreas.Sandberg@ARM.com * There are currently two different atomic memory modes: 1409524SAndreas.Sandberg@ARM.com * 'atomic', which supports caches; and 'atomic_noncaching', which 1419524SAndreas.Sandberg@ARM.com * bypasses caches. The latter is used by hardware virtualized 1429524SAndreas.Sandberg@ARM.com * CPUs. SimObjects are expected to use Port::sendAtomic() and 1439524SAndreas.Sandberg@ARM.com * Port::recvAtomic() when accessing memory in this mode. 1449524SAndreas.Sandberg@ARM.com */ 1459524SAndreas.Sandberg@ARM.com bool isAtomicMode() const { 1469524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic || 1479524SAndreas.Sandberg@ARM.com memoryMode == Enums::atomic_noncaching; 1484762Snate@binkert.org } 1492901Ssaidi@eecs.umich.edu 1509524SAndreas.Sandberg@ARM.com /** 1519524SAndreas.Sandberg@ARM.com * Is the system in timing mode? 1529524SAndreas.Sandberg@ARM.com * 1539524SAndreas.Sandberg@ARM.com * SimObjects are expected to use Port::sendTiming() and 1549524SAndreas.Sandberg@ARM.com * Port::recvTiming() when accessing memory in this mode. 1559524SAndreas.Sandberg@ARM.com */ 1569524SAndreas.Sandberg@ARM.com bool isTimingMode() const { 1579524SAndreas.Sandberg@ARM.com return memoryMode == Enums::timing; 1589524SAndreas.Sandberg@ARM.com } 1599524SAndreas.Sandberg@ARM.com 1609524SAndreas.Sandberg@ARM.com /** 1619524SAndreas.Sandberg@ARM.com * Should caches be bypassed? 1629524SAndreas.Sandberg@ARM.com * 1639524SAndreas.Sandberg@ARM.com * Some CPUs need to bypass caches to allow direct memory 1649524SAndreas.Sandberg@ARM.com * accesses, which is required for hardware virtualization. 1659524SAndreas.Sandberg@ARM.com */ 1669524SAndreas.Sandberg@ARM.com bool bypassCaches() const { 1679524SAndreas.Sandberg@ARM.com return memoryMode == Enums::atomic_noncaching; 1689524SAndreas.Sandberg@ARM.com } 1699524SAndreas.Sandberg@ARM.com /** @} */ 1709524SAndreas.Sandberg@ARM.com 1719524SAndreas.Sandberg@ARM.com /** @{ */ 1729524SAndreas.Sandberg@ARM.com /** 1739524SAndreas.Sandberg@ARM.com * Get the memory mode of the system. 1749524SAndreas.Sandberg@ARM.com * 1759524SAndreas.Sandberg@ARM.com * \warn This should only be used by the Python world. The C++ 1769524SAndreas.Sandberg@ARM.com * world should use one of the query functions above 1779524SAndreas.Sandberg@ARM.com * (isAtomicMode(), isTimingMode(), bypassCaches()). 1789524SAndreas.Sandberg@ARM.com */ 1799524SAndreas.Sandberg@ARM.com Enums::MemoryMode getMemoryMode() const { return memoryMode; } 1809524SAndreas.Sandberg@ARM.com 1819524SAndreas.Sandberg@ARM.com /** 1829524SAndreas.Sandberg@ARM.com * Change the memory mode of the system. 1839524SAndreas.Sandberg@ARM.com * 1849524SAndreas.Sandberg@ARM.com * \warn This should only be called by the Python! 1859524SAndreas.Sandberg@ARM.com * 1869524SAndreas.Sandberg@ARM.com * @param mode Mode to change to (atomic/timing/...) 1872901Ssaidi@eecs.umich.edu */ 1884762Snate@binkert.org void setMemoryMode(Enums::MemoryMode mode); 1899524SAndreas.Sandberg@ARM.com /** @} */ 1902901Ssaidi@eecs.umich.edu 1919814Sandreas.hansson@arm.com /** 1929814Sandreas.hansson@arm.com * Get the cache line size of the system. 1939814Sandreas.hansson@arm.com */ 1949814Sandreas.hansson@arm.com unsigned int cacheLineSize() const { return _cacheLineSize; } 1959814Sandreas.hansson@arm.com 1969850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 1972SN/A PCEventQueue pcEventQueue; 1989850Sandreas.hansson@arm.com#endif 1992SN/A 2002680Sktlim@umich.edu std::vector<ThreadContext *> threadContexts; 20111146Smitch.hayenga@arm.com const bool multiThread; 2021806SN/A 20311005Sandreas.sandberg@arm.com ThreadContext *getThreadContext(ContextID tid) 2045713Shsul@eecs.umich.edu { 2055713Shsul@eecs.umich.edu return threadContexts[tid]; 2065713Shsul@eecs.umich.edu } 2075713Shsul@eecs.umich.edu 20812515Sgiacomo.travaglini@arm.com unsigned numContexts() const { return threadContexts.size(); } 209180SN/A 2106029Ssteve.reinhardt@amd.com /** Return number of running (non-halted) thread contexts in 2116029Ssteve.reinhardt@amd.com * system. These threads could be Active or Suspended. */ 2126029Ssteve.reinhardt@amd.com int numRunningContexts(); 2136029Ssteve.reinhardt@amd.com 2148765Sgblack@eecs.umich.edu Addr pagePtr; 2158765Sgblack@eecs.umich.edu 2162378SN/A uint64_t init_param; 2172378SN/A 2182520SN/A /** Port to physical memory used for writing object files into ram at 2192520SN/A * boot.*/ 2208852Sandreas.hansson@arm.com PortProxy physProxy; 2212520SN/A 2221885SN/A /** kernel symbol table */ 2231070SN/A SymbolTable *kernelSymtab; 224954SN/A 2251070SN/A /** Object pointer for the kernel code */ 2261070SN/A ObjectFile *kernel; 2271070SN/A 22812262Sandreas.sandberg@arm.com /** Additional object files */ 22912262Sandreas.sandberg@arm.com std::vector<ObjectFile *> kernelExtras; 23012262Sandreas.sandberg@arm.com 23111838SCurtis.Dunham@arm.com /** Beginning of kernel code */ 2321070SN/A Addr kernelStart; 2331070SN/A 2341070SN/A /** End of kernel code */ 2351070SN/A Addr kernelEnd; 2361070SN/A 2371070SN/A /** Entry point in the kernel to start at */ 2381070SN/A Addr kernelEntry; 2391070SN/A 2407580SAli.Saidi@arm.com /** Mask that should be anded for binary/symbol loading. 2417580SAli.Saidi@arm.com * This allows one two different OS requirements for the same ISA to be 2427580SAli.Saidi@arm.com * handled. Some OSes are compiled for a virtual address and need to be 2437580SAli.Saidi@arm.com * loaded into physical memory that starts at address 0, while other 2447580SAli.Saidi@arm.com * bare metal tools generate images that start at address 0. 2457580SAli.Saidi@arm.com */ 2467580SAli.Saidi@arm.com Addr loadAddrMask; 2477580SAli.Saidi@arm.com 24810037SARM gem5 Developers /** Offset that should be used for binary/symbol loading. 24911838SCurtis.Dunham@arm.com * This further allows more flexibility than the loadAddrMask allows alone 25011838SCurtis.Dunham@arm.com * in loading kernels and similar. The loadAddrOffset is applied after the 25110037SARM gem5 Developers * loadAddrMask. 25210037SARM gem5 Developers */ 25310037SARM gem5 Developers Addr loadAddrOffset; 25410037SARM gem5 Developers 2554997Sgblack@eecs.umich.edu public: 25611839SCurtis.Dunham@arm.com /** 25711839SCurtis.Dunham@arm.com * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 25811839SCurtis.Dunham@arm.com * if present. 25911839SCurtis.Dunham@arm.com */ 26011839SCurtis.Dunham@arm.com KvmVM* getKvmVM() { 26111839SCurtis.Dunham@arm.com return kvmVM; 26211839SCurtis.Dunham@arm.com } 26311839SCurtis.Dunham@arm.com 26412100SCurtis.Dunham@arm.com /** Verify gem5 configuration will support KVM emulation */ 26512100SCurtis.Dunham@arm.com bool validKvmEnvironment() const; 26612100SCurtis.Dunham@arm.com 2678931Sandreas.hansson@arm.com /** Get a pointer to access the physical memory of the system */ 2688931Sandreas.hansson@arm.com PhysicalMemory& getPhysMem() { return physmem; } 2698931Sandreas.hansson@arm.com 2705795Ssaidi@eecs.umich.edu /** Amount of physical memory that is still free */ 2718931Sandreas.hansson@arm.com Addr freeMemSize() const; 2725795Ssaidi@eecs.umich.edu 2735795Ssaidi@eecs.umich.edu /** Amount of physical memory that exists */ 2748931Sandreas.hansson@arm.com Addr memSize() const; 2758931Sandreas.hansson@arm.com 2768931Sandreas.hansson@arm.com /** 2778931Sandreas.hansson@arm.com * Check if a physical address is within a range of a memory that 2788931Sandreas.hansson@arm.com * is part of the global address map. 2798931Sandreas.hansson@arm.com * 2808931Sandreas.hansson@arm.com * @param addr A physical address 2818931Sandreas.hansson@arm.com * @return Whether the address corresponds to a memory 2828931Sandreas.hansson@arm.com */ 2838931Sandreas.hansson@arm.com bool isMemAddr(Addr addr) const; 2845795Ssaidi@eecs.umich.edu 28510467Sandreas.hansson@arm.com /** 28610467Sandreas.hansson@arm.com * Get the architecture. 28710467Sandreas.hansson@arm.com */ 28810467Sandreas.hansson@arm.com Arch getArch() const { return Arch::TheISA; } 28910467Sandreas.hansson@arm.com 29010466Sandreas.hansson@arm.com /** 29110466Sandreas.hansson@arm.com * Get the page bytes for the ISA. 29210466Sandreas.hansson@arm.com */ 29310466Sandreas.hansson@arm.com Addr getPageBytes() const { return TheISA::PageBytes; } 29410466Sandreas.hansson@arm.com 29510466Sandreas.hansson@arm.com /** 29611838SCurtis.Dunham@arm.com * Get the number of bits worth of in-page address for the ISA. 29710466Sandreas.hansson@arm.com */ 29810466Sandreas.hansson@arm.com Addr getPageShift() const { return TheISA::PageShift; } 29910466Sandreas.hansson@arm.com 30011420Sdavid.guillen@arm.com /** 30111420Sdavid.guillen@arm.com * The thermal model used for this system (if any). 30211420Sdavid.guillen@arm.com */ 30311420Sdavid.guillen@arm.com ThermalModel * getThermalModel() const { return thermalModel; } 30411420Sdavid.guillen@arm.com 3051885SN/A protected: 3068931Sandreas.hansson@arm.com 30711839SCurtis.Dunham@arm.com KvmVM *const kvmVM; 30811839SCurtis.Dunham@arm.com 3098931Sandreas.hansson@arm.com PhysicalMemory physmem; 3108931Sandreas.hansson@arm.com 3114762Snate@binkert.org Enums::MemoryMode memoryMode; 3129814Sandreas.hansson@arm.com 3139814Sandreas.hansson@arm.com const unsigned int _cacheLineSize; 3149814Sandreas.hansson@arm.com 3157914SBrad.Beckmann@amd.com uint64_t workItemsBegin; 3167914SBrad.Beckmann@amd.com uint64_t workItemsEnd; 3178666SPrakash.Ramrakhyani@arm.com uint32_t numWorkIds; 3187914SBrad.Beckmann@amd.com std::vector<bool> activeCpus; 3197914SBrad.Beckmann@amd.com 32011838SCurtis.Dunham@arm.com /** This array is a per-system list of all devices capable of issuing a 3218832SAli.Saidi@ARM.com * memory system request and an associated string for each master id. 3228832SAli.Saidi@ARM.com * It's used to uniquely id any master in the system by name for things 3238832SAli.Saidi@ARM.com * like cache statistics. 3248832SAli.Saidi@ARM.com */ 32512680Sgiacomo.travaglini@arm.com std::vector<MasterInfo> masters; 3268832SAli.Saidi@ARM.com 32711420Sdavid.guillen@arm.com ThermalModel * thermalModel; 32811420Sdavid.guillen@arm.com 32912965Sgiacomo.travaglini@arm.com protected: 33012965Sgiacomo.travaglini@arm.com /** 33112965Sgiacomo.travaglini@arm.com * Strips off the system name from a master name 33212965Sgiacomo.travaglini@arm.com */ 33312965Sgiacomo.travaglini@arm.com std::string stripSystemName(const std::string& master_name) const; 33412965Sgiacomo.travaglini@arm.com 3357914SBrad.Beckmann@amd.com public: 3368832SAli.Saidi@ARM.com 33712680Sgiacomo.travaglini@arm.com /** 33812680Sgiacomo.travaglini@arm.com * Request an id used to create a request object in the system. All objects 3398832SAli.Saidi@ARM.com * that intend to issues requests into the memory system must request an id 3408832SAli.Saidi@ARM.com * in the init() phase of startup. All master ids must be fixed by the 34111838SCurtis.Dunham@arm.com * regStats() phase that immediately precedes it. This allows objects in 34211838SCurtis.Dunham@arm.com * the memory system to understand how many masters may exist and 3438832SAli.Saidi@ARM.com * appropriately name the bins of their per-master stats before the stats 34412680Sgiacomo.travaglini@arm.com * are finalized. 34512680Sgiacomo.travaglini@arm.com * 34612680Sgiacomo.travaglini@arm.com * Registers a MasterID: 34712680Sgiacomo.travaglini@arm.com * This method takes two parameters, one of which is optional. 34812680Sgiacomo.travaglini@arm.com * The first one is the master object, and it is compulsory; in case 34912680Sgiacomo.travaglini@arm.com * a object has multiple (sub)masters, a second parameter must be 35012680Sgiacomo.travaglini@arm.com * provided and it contains the name of the submaster. The method will 35112680Sgiacomo.travaglini@arm.com * create a master's name by concatenating the SimObject name with the 35212680Sgiacomo.travaglini@arm.com * eventual submaster string, separated by a dot. 35312680Sgiacomo.travaglini@arm.com * 35412680Sgiacomo.travaglini@arm.com * As an example: 35512680Sgiacomo.travaglini@arm.com * For a cpu having two masters: a data master and an instruction master, 35612680Sgiacomo.travaglini@arm.com * the method must be called twice: 35712680Sgiacomo.travaglini@arm.com * 35812680Sgiacomo.travaglini@arm.com * instMasterId = getMasterId(cpu, "inst"); 35912680Sgiacomo.travaglini@arm.com * dataMasterId = getMasterId(cpu, "data"); 36012680Sgiacomo.travaglini@arm.com * 36112680Sgiacomo.travaglini@arm.com * and the masters' names will be: 36212680Sgiacomo.travaglini@arm.com * - "cpu.inst" 36312680Sgiacomo.travaglini@arm.com * - "cpu.data" 36412680Sgiacomo.travaglini@arm.com * 36512680Sgiacomo.travaglini@arm.com * @param master SimObject related to the master 36612680Sgiacomo.travaglini@arm.com * @param submaster String containing the submaster's name 36712680Sgiacomo.travaglini@arm.com * @return the master's ID. 3688832SAli.Saidi@ARM.com */ 36912680Sgiacomo.travaglini@arm.com MasterID getMasterId(const SimObject* master, 37012680Sgiacomo.travaglini@arm.com std::string submaster = std::string()); 3718832SAli.Saidi@ARM.com 37212680Sgiacomo.travaglini@arm.com /** 37312680Sgiacomo.travaglini@arm.com * Registers a GLOBAL MasterID, which is a MasterID not related 37412680Sgiacomo.travaglini@arm.com * to any particular SimObject; since no SimObject is passed, 37512680Sgiacomo.travaglini@arm.com * the master gets registered by providing the full master name. 37612680Sgiacomo.travaglini@arm.com * 37712680Sgiacomo.travaglini@arm.com * @param masterName full name of the master 37812680Sgiacomo.travaglini@arm.com * @return the master's ID. 37912680Sgiacomo.travaglini@arm.com */ 38012965Sgiacomo.travaglini@arm.com MasterID getGlobalMasterId(const std::string& master_name); 38112680Sgiacomo.travaglini@arm.com 38212680Sgiacomo.travaglini@arm.com /** 38312680Sgiacomo.travaglini@arm.com * Get the name of an object for a given request id. 3848832SAli.Saidi@ARM.com */ 3858832SAli.Saidi@ARM.com std::string getMasterName(MasterID master_id); 3868832SAli.Saidi@ARM.com 38712965Sgiacomo.travaglini@arm.com /** 38812965Sgiacomo.travaglini@arm.com * Looks up the MasterID for a given SimObject 38912965Sgiacomo.travaglini@arm.com * returns an invalid MasterID (invldMasterId) if not found. 39012965Sgiacomo.travaglini@arm.com */ 39112965Sgiacomo.travaglini@arm.com MasterID lookupMasterId(const SimObject* obj) const; 39212965Sgiacomo.travaglini@arm.com 39312965Sgiacomo.travaglini@arm.com /** 39412965Sgiacomo.travaglini@arm.com * Looks up the MasterID for a given object name string 39512965Sgiacomo.travaglini@arm.com * returns an invalid MasterID (invldMasterId) if not found. 39612965Sgiacomo.travaglini@arm.com */ 39712965Sgiacomo.travaglini@arm.com MasterID lookupMasterId(const std::string& name) const; 39812965Sgiacomo.travaglini@arm.com 3998832SAli.Saidi@ARM.com /** Get the number of masters registered in the system */ 40012680Sgiacomo.travaglini@arm.com MasterID maxMasters() { return masters.size(); } 40112680Sgiacomo.travaglini@arm.com 40212680Sgiacomo.travaglini@arm.com protected: 40312680Sgiacomo.travaglini@arm.com /** helper function for getMasterId */ 40412965Sgiacomo.travaglini@arm.com MasterID _getMasterId(const SimObject* master, 40512965Sgiacomo.travaglini@arm.com const std::string& master_name); 40612680Sgiacomo.travaglini@arm.com 40712680Sgiacomo.travaglini@arm.com /** 40812680Sgiacomo.travaglini@arm.com * Helper function for constructing the full (sub)master name 40912680Sgiacomo.travaglini@arm.com * by providing the root master and the relative submaster name. 41012680Sgiacomo.travaglini@arm.com */ 41112680Sgiacomo.travaglini@arm.com std::string leafMasterName(const SimObject* master, 41212680Sgiacomo.travaglini@arm.com const std::string& submaster); 41312680Sgiacomo.travaglini@arm.com 41412680Sgiacomo.travaglini@arm.com public: 4158832SAli.Saidi@ARM.com 41611169Sandreas.hansson@arm.com void regStats() override; 4177914SBrad.Beckmann@amd.com /** 4187914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items started by this 4197914SBrad.Beckmann@amd.com * system. 4207914SBrad.Beckmann@amd.com */ 4218666SPrakash.Ramrakhyani@arm.com uint64_t 4227914SBrad.Beckmann@amd.com incWorkItemsBegin() 4237914SBrad.Beckmann@amd.com { 4247914SBrad.Beckmann@amd.com return ++workItemsBegin; 4257914SBrad.Beckmann@amd.com } 4267914SBrad.Beckmann@amd.com 4277914SBrad.Beckmann@amd.com /** 4287914SBrad.Beckmann@amd.com * Called by pseudo_inst to track the number of work items completed by 4297914SBrad.Beckmann@amd.com * this system. 4307914SBrad.Beckmann@amd.com */ 43110037SARM gem5 Developers uint64_t 4327914SBrad.Beckmann@amd.com incWorkItemsEnd() 4337914SBrad.Beckmann@amd.com { 4347914SBrad.Beckmann@amd.com return ++workItemsEnd; 4357914SBrad.Beckmann@amd.com } 4367914SBrad.Beckmann@amd.com 4377914SBrad.Beckmann@amd.com /** 4387914SBrad.Beckmann@amd.com * Called by pseudo_inst to mark the cpus actively executing work items. 4397914SBrad.Beckmann@amd.com * Returns the total number of cpus that have executed work item begin or 4407914SBrad.Beckmann@amd.com * ends. 4417914SBrad.Beckmann@amd.com */ 44210037SARM gem5 Developers int 4437914SBrad.Beckmann@amd.com markWorkItem(int index) 4447914SBrad.Beckmann@amd.com { 4457914SBrad.Beckmann@amd.com int count = 0; 4467914SBrad.Beckmann@amd.com assert(index < activeCpus.size()); 4477914SBrad.Beckmann@amd.com activeCpus[index] = true; 44810037SARM gem5 Developers for (std::vector<bool>::iterator i = activeCpus.begin(); 4497914SBrad.Beckmann@amd.com i < activeCpus.end(); i++) { 4507914SBrad.Beckmann@amd.com if (*i) count++; 4517914SBrad.Beckmann@amd.com } 4527914SBrad.Beckmann@amd.com return count; 4537914SBrad.Beckmann@amd.com } 4542901Ssaidi@eecs.umich.edu 4558666SPrakash.Ramrakhyani@arm.com inline void workItemBegin(uint32_t tid, uint32_t workid) 4568666SPrakash.Ramrakhyani@arm.com { 4578666SPrakash.Ramrakhyani@arm.com std::pair<uint32_t,uint32_t> p(tid, workid); 4588666SPrakash.Ramrakhyani@arm.com lastWorkItemStarted[p] = curTick(); 4598666SPrakash.Ramrakhyani@arm.com } 4608666SPrakash.Ramrakhyani@arm.com 4618666SPrakash.Ramrakhyani@arm.com void workItemEnd(uint32_t tid, uint32_t workid); 4628666SPrakash.Ramrakhyani@arm.com 4631885SN/A /** 4641885SN/A * Fix up an address used to match PCs for hooking simulator 4651885SN/A * events on to target function executions. See comment in 4661885SN/A * system.cc for details. 4671885SN/A */ 4688769Sgblack@eecs.umich.edu virtual Addr fixFuncEventAddr(Addr addr) 4698769Sgblack@eecs.umich.edu { 4708769Sgblack@eecs.umich.edu panic("Base fixFuncEventAddr not implemented.\n"); 4718769Sgblack@eecs.umich.edu } 4721885SN/A 4739645SAndreas.Sandberg@ARM.com /** @{ */ 4741885SN/A /** 4751885SN/A * Add a function-based event to the given function, to be looked 4761885SN/A * up in the specified symbol table. 4779645SAndreas.Sandberg@ARM.com * 4789645SAndreas.Sandberg@ARM.com * The ...OrPanic flavor of the method causes the simulator to 4799645SAndreas.Sandberg@ARM.com * panic if the symbol can't be found. 4809645SAndreas.Sandberg@ARM.com * 4819645SAndreas.Sandberg@ARM.com * @param symtab Symbol table to use for look up. 4829645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 4839645SAndreas.Sandberg@ARM.com * @param desc Description to be passed to the event. 4849645SAndreas.Sandberg@ARM.com * @param args Arguments to be forwarded to the event constructor. 4851885SN/A */ 4869645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 4879645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 4889645SAndreas.Sandberg@ARM.com const std::string &desc, Args... args) 4891885SN/A { 4909855Sandreas.hansson@arm.com Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 4911885SN/A 4929850Sandreas.hansson@arm.com#if THE_ISA != NULL_ISA 4931885SN/A if (symtab->findAddress(lbl, addr)) { 4949645SAndreas.Sandberg@ARM.com T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 4959645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 4961885SN/A return ev; 4971885SN/A } 4989850Sandreas.hansson@arm.com#endif 4991885SN/A 5001885SN/A return NULL; 5011885SN/A } 5021885SN/A 5031885SN/A template <class T> 5049645SAndreas.Sandberg@ARM.com T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 5051885SN/A { 5069645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(symtab, lbl, lbl); 5071885SN/A } 5081885SN/A 5099645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 5109645SAndreas.Sandberg@ARM.com T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 5119645SAndreas.Sandberg@ARM.com Args... args) 5129645SAndreas.Sandberg@ARM.com { 5139645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 5149645SAndreas.Sandberg@ARM.com if (!e) 5159645SAndreas.Sandberg@ARM.com panic("Failed to find symbol '%s'", lbl); 5169645SAndreas.Sandberg@ARM.com return e; 5179645SAndreas.Sandberg@ARM.com } 5189645SAndreas.Sandberg@ARM.com /** @} */ 5199645SAndreas.Sandberg@ARM.com 5209645SAndreas.Sandberg@ARM.com /** @{ */ 5219645SAndreas.Sandberg@ARM.com /** 5229645SAndreas.Sandberg@ARM.com * Add a function-based event to a kernel symbol. 5239645SAndreas.Sandberg@ARM.com * 5249645SAndreas.Sandberg@ARM.com * These functions work like their addFuncEvent() and 5259645SAndreas.Sandberg@ARM.com * addFuncEventOrPanic() counterparts. The only difference is that 5269645SAndreas.Sandberg@ARM.com * they automatically use the kernel symbol table. All arguments 5279645SAndreas.Sandberg@ARM.com * are forwarded to the underlying method. 5289645SAndreas.Sandberg@ARM.com * 5299645SAndreas.Sandberg@ARM.com * @see addFuncEvent() 5309645SAndreas.Sandberg@ARM.com * @see addFuncEventOrPanic() 5319645SAndreas.Sandberg@ARM.com * 5329645SAndreas.Sandberg@ARM.com * @param lbl Function to hook the event to. 5339645SAndreas.Sandberg@ARM.com * @param args Arguments to be passed to addFuncEvent 5349645SAndreas.Sandberg@ARM.com */ 5359645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 5369645SAndreas.Sandberg@ARM.com T *addKernelFuncEvent(const char *lbl, Args... args) 5379645SAndreas.Sandberg@ARM.com { 5389645SAndreas.Sandberg@ARM.com return addFuncEvent<T>(kernelSymtab, lbl, 5399645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...); 5409645SAndreas.Sandberg@ARM.com } 5419645SAndreas.Sandberg@ARM.com 5429645SAndreas.Sandberg@ARM.com template <class T, typename... Args> 5439645SAndreas.Sandberg@ARM.com T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 5449645SAndreas.Sandberg@ARM.com { 5459645SAndreas.Sandberg@ARM.com T *e(addFuncEvent<T>(kernelSymtab, lbl, 5469645SAndreas.Sandberg@ARM.com std::forward<Args>(args)...)); 5479645SAndreas.Sandberg@ARM.com if (!e) 5489645SAndreas.Sandberg@ARM.com panic("Failed to find kernel symbol '%s'", lbl); 5499645SAndreas.Sandberg@ARM.com return e; 5509645SAndreas.Sandberg@ARM.com } 5519645SAndreas.Sandberg@ARM.com /** @} */ 5529645SAndreas.Sandberg@ARM.com 55377SN/A public: 5546658Snate@binkert.org std::vector<BaseRemoteGDB *> remoteGDB; 5553960Sgblack@eecs.umich.edu bool breakpoint(); 5561070SN/A 5571070SN/A public: 5584762Snate@binkert.org typedef SystemParams Params; 5591070SN/A 5602158SN/A protected: 5612158SN/A Params *_params; 5621070SN/A 5632158SN/A public: 5641070SN/A System(Params *p); 5652SN/A ~System(); 5662SN/A 56711169Sandreas.hansson@arm.com void initState() override; 5681129SN/A 5692158SN/A const Params *params() const { return (const Params *)_params; } 5702158SN/A 5711070SN/A public: 5722378SN/A 5731070SN/A /** 57411838SCurtis.Dunham@arm.com * Returns the address the kernel starts at. 5751070SN/A * @return address the kernel starts at 5761070SN/A */ 5771070SN/A Addr getKernelStart() const { return kernelStart; } 5781070SN/A 5791070SN/A /** 58011838SCurtis.Dunham@arm.com * Returns the address the kernel ends at. 5811070SN/A * @return address the kernel ends at 5821070SN/A */ 5831070SN/A Addr getKernelEnd() const { return kernelEnd; } 5841070SN/A 5851070SN/A /** 58611838SCurtis.Dunham@arm.com * Returns the address the entry point to the kernel code. 5871070SN/A * @return entry point of the kernel code 5881070SN/A */ 5891070SN/A Addr getKernelEntry() const { return kernelEntry; } 5901070SN/A 5918601Ssteve.reinhardt@amd.com /// Allocate npages contiguous unused physical pages 5928601Ssteve.reinhardt@amd.com /// @return Starting address of first page 5938601Ssteve.reinhardt@amd.com Addr allocPhysPages(int npages); 5942378SN/A 59511005Sandreas.sandberg@arm.com ContextID registerThreadContext(ThreadContext *tc, 59611005Sandreas.sandberg@arm.com ContextID assigned = InvalidContextID); 59711005Sandreas.sandberg@arm.com void replaceThreadContext(ThreadContext *tc, ContextID context_id); 5981070SN/A 59911168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 60011168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 6019342SAndreas.Sandberg@arm.com 60211168Sandreas.hansson@arm.com void drainResume() override; 6032SN/A 60477SN/A public: 6057897Shestness@cs.utexas.edu Counter totalNumInsts; 6067897Shestness@cs.utexas.edu EventQueue instEventQueue; 6078666SPrakash.Ramrakhyani@arm.com std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 6088666SPrakash.Ramrakhyani@arm.com std::map<uint32_t, Stats::Histogram*> workItemStats; 6097897Shestness@cs.utexas.edu 6102SN/A //////////////////////////////////////////// 6112SN/A // 6122SN/A // STATIC GLOBAL SYSTEM LIST 6132SN/A // 6142SN/A //////////////////////////////////////////// 6152SN/A 6162SN/A static std::vector<System *> systemList; 6172SN/A static int numSystemsRunning; 6182SN/A 6192SN/A static void printSystems(); 6202158SN/A 62111911SBrandon.Potter@amd.com FutexMap futexMap; 6229112Smarc.orr@gmail.com 62311885Sbrandon.potter@amd.com static const int maxPID = 32768; 62411885Sbrandon.potter@amd.com 62511885Sbrandon.potter@amd.com /** Process set to track which PIDs have already been allocated */ 62611885Sbrandon.potter@amd.com std::set<int> PIDs; 62711885Sbrandon.potter@amd.com 62811909SBrandon.Potter@amd.com // By convention, all signals are owned by the receiving process. The 62911909SBrandon.Potter@amd.com // receiver will delete the signal upon reception. 63011909SBrandon.Potter@amd.com std::list<BasicSignal> signalList; 63111909SBrandon.Potter@amd.com 63213883Sdavid.hashe@amd.com // Used by syscall-emulation mode. This member contains paths which need 63313883Sdavid.hashe@amd.com // to be redirected to the faux-filesystem (a duplicate filesystem 63413883Sdavid.hashe@amd.com // intended to replace certain files on the host filesystem). 63513883Sdavid.hashe@amd.com std::vector<RedirectPath*> redirectPaths; 63613883Sdavid.hashe@amd.com 6379292Sandreas.hansson@arm.com protected: 6389292Sandreas.hansson@arm.com 6399292Sandreas.hansson@arm.com /** 6409292Sandreas.hansson@arm.com * If needed, serialize additional symbol table entries for a 64111838SCurtis.Dunham@arm.com * specific subclass of this system. Currently this is used by 6429292Sandreas.hansson@arm.com * Alpha and MIPS. 6439292Sandreas.hansson@arm.com * 6449292Sandreas.hansson@arm.com * @param os stream to serialize to 6459292Sandreas.hansson@arm.com */ 64610905Sandreas.sandberg@arm.com virtual void serializeSymtab(CheckpointOut &os) const {} 6479292Sandreas.hansson@arm.com 6489292Sandreas.hansson@arm.com /** 6499292Sandreas.hansson@arm.com * If needed, unserialize additional symbol table entries for a 6509292Sandreas.hansson@arm.com * specific subclass of this system. 6519292Sandreas.hansson@arm.com * 6529292Sandreas.hansson@arm.com * @param cp checkpoint to unserialize from 6539292Sandreas.hansson@arm.com * @param section relevant section in the checkpoint 6549292Sandreas.hansson@arm.com */ 65510905Sandreas.sandberg@arm.com virtual void unserializeSymtab(CheckpointIn &cp) {} 6562SN/A}; 6572SN/A 6589554Sandreas.hansson@arm.comvoid printSystems(); 6599554Sandreas.hansson@arm.com 6602SN/A#endif // __SYSTEM_HH__ 661