112726Snikos.nikoleris@arm.com# Copyright (c) 2015, 2018 ARM Limited
210690Sandreas.hansson@arm.com# All rights reserved.
310690Sandreas.hansson@arm.com#
410690Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
510690Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
610690Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
710690Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
810690Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
910690Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
1010690Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
1110690Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form.
1210690Sandreas.hansson@arm.com#
134467Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
143354Srdreslin@umich.edu# All rights reserved.
153354Srdreslin@umich.edu#
163354Srdreslin@umich.edu# Redistribution and use in source and binary forms, with or without
173354Srdreslin@umich.edu# modification, are permitted provided that the following conditions are
183354Srdreslin@umich.edu# met: redistributions of source code must retain the above copyright
193354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer;
203354Srdreslin@umich.edu# redistributions in binary form must reproduce the above copyright
213354Srdreslin@umich.edu# notice, this list of conditions and the following disclaimer in the
223354Srdreslin@umich.edu# documentation and/or other materials provided with the distribution;
233354Srdreslin@umich.edu# neither the name of the copyright holders nor the names of its
243354Srdreslin@umich.edu# contributors may be used to endorse or promote products derived from
253354Srdreslin@umich.edu# this software without specific prior written permission.
263354Srdreslin@umich.edu#
273354Srdreslin@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283354Srdreslin@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293354Srdreslin@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303354Srdreslin@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313354Srdreslin@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323354Srdreslin@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333354Srdreslin@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343354Srdreslin@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353354Srdreslin@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363354Srdreslin@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373354Srdreslin@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383354Srdreslin@umich.edu#
393354Srdreslin@umich.edu# Authors: Ron Dreslinski
4010690Sandreas.hansson@arm.com#          Andreas Hansson
413354Srdreslin@umich.edu
4212564Sgabeblack@google.comfrom __future__ import print_function
4313774Sandreas.sandberg@arm.comfrom __future__ import absolute_import
4412564Sgabeblack@google.com
456654Snate@binkert.orgimport optparse
4610750Sandreas.hansson@arm.comimport random
476654Snate@binkert.orgimport sys
486654Snate@binkert.org
493354Srdreslin@umich.eduimport m5
503354Srdreslin@umich.edufrom m5.objects import *
513354Srdreslin@umich.edu
5210750Sandreas.hansson@arm.com# This example script stress tests the memory system by creating false
5310750Sandreas.hansson@arm.com# sharing in a tree topology. At the bottom of the tree is a shared
5410750Sandreas.hansson@arm.com# memory, and then at each level a number of testers are attached,
5510750Sandreas.hansson@arm.com# along with a number of caches that them selves fan out to subtrees
5610750Sandreas.hansson@arm.com# of testers and caches. Thus, it is possible to create a system with
5710750Sandreas.hansson@arm.com# arbitrarily deep cache hierarchies, sharing or no sharing of caches,
5810750Sandreas.hansson@arm.com# and testers not only at the L1s, but also at the L2s, L3s etc.
5910750Sandreas.hansson@arm.com
603354Srdreslin@umich.eduparser = optparse.OptionParser()
613354Srdreslin@umich.edu
624626Sstever@eecs.umich.eduparser.add_option("-a", "--atomic", action="store_true",
634626Sstever@eecs.umich.edu                  help="Use atomic (non-timing) mode")
644626Sstever@eecs.umich.eduparser.add_option("-b", "--blocking", action="store_true",
654626Sstever@eecs.umich.edu                  help="Use blocking caches")
664893Sstever@eecs.umich.eduparser.add_option("-l", "--maxloads", metavar="N", default=0,
674892Sstever@eecs.umich.edu                  help="Stop after N loads")
684626Sstever@eecs.umich.eduparser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
694626Sstever@eecs.umich.edu                  metavar="T",
704626Sstever@eecs.umich.edu                  help="Stop after T ticks")
714626Sstever@eecs.umich.edu
7210690Sandreas.hansson@arm.com# The tree specification consists of two colon-separated lists of one
7310690Sandreas.hansson@arm.com# or more integers, one for the caches, and one for the testers. The
7410690Sandreas.hansson@arm.com# first integer is the number of caches/testers closest to main
7510690Sandreas.hansson@arm.com# memory. Each cache then fans out to a subtree. The last integer in
7610690Sandreas.hansson@arm.com# the list is the number of caches/testers associated with the
7710690Sandreas.hansson@arm.com# uppermost level of memory. The other integers (if any) specify the
7810690Sandreas.hansson@arm.com# number of caches/testers connected at each level of the crossbar
7910690Sandreas.hansson@arm.com# hierarchy. The tester string should have one element more than the
8010690Sandreas.hansson@arm.com# cache string as there should always be testers attached to the
8110690Sandreas.hansson@arm.com# uppermost caches.
8210690Sandreas.hansson@arm.com
8310690Sandreas.hansson@arm.comparser.add_option("-c", "--caches", type="string", default="2:2:1",
8410690Sandreas.hansson@arm.com                  help="Colon-separated cache hierarchy specification, "
854892Sstever@eecs.umich.edu                  "see script comments for details "
864892Sstever@eecs.umich.edu                  "[default: %default]")
8712726Snikos.nikoleris@arm.comparser.add_option("--noncoherent-cache", action="store_true",
8812726Snikos.nikoleris@arm.com                  help="Adds a non-coherent, last-level cache")
8910690Sandreas.hansson@arm.comparser.add_option("-t", "--testers", type="string", default="1:1:0:2",
9010690Sandreas.hansson@arm.com                  help="Colon-separated tester hierarchy specification, "
9110690Sandreas.hansson@arm.com                  "see script comments for details "
9210690Sandreas.hansson@arm.com                  "[default: %default]")
9311272Sandreas.hansson@arm.comparser.add_option("-f", "--functional", type="int", default=10,
944626Sstever@eecs.umich.edu                  metavar="PCT",
954626Sstever@eecs.umich.edu                  help="Target percentage of functional accesses "
964626Sstever@eecs.umich.edu                  "[default: %default]")
9711272Sandreas.hansson@arm.comparser.add_option("-u", "--uncacheable", type="int", default=10,
984626Sstever@eecs.umich.edu                  metavar="PCT",
994626Sstever@eecs.umich.edu                  help="Target percentage of uncacheable accesses "
1004626Sstever@eecs.umich.edu                  "[default: %default]")
10110750Sandreas.hansson@arm.comparser.add_option("-r", "--random", action="store_true",
10210750Sandreas.hansson@arm.com                  help="Generate a random tree topology")
10310750Sandreas.hansson@arm.comparser.add_option("--progress", type="int", default=100000,
1044628Sstever@eecs.umich.edu                  metavar="NLOADS",
1054628Sstever@eecs.umich.edu                  help="Progress message interval "
1064628Sstever@eecs.umich.edu                  "[default: %default]")
1079928SAli.Saidi@ARM.comparser.add_option("--sys-clock", action="store", type="string",
1089928SAli.Saidi@ARM.com                  default='1GHz',
1099928SAli.Saidi@ARM.com                  help = """Top-level clock for blocks running at system
1109928SAli.Saidi@ARM.com                  speed""")
1114628Sstever@eecs.umich.edu
1123354Srdreslin@umich.edu(options, args) = parser.parse_args()
1133354Srdreslin@umich.edu
1143354Srdreslin@umich.eduif args:
11512564Sgabeblack@google.com     print("Error: script doesn't take any positional arguments")
1163354Srdreslin@umich.edu     sys.exit(1)
1173354Srdreslin@umich.edu
11810750Sandreas.hansson@arm.com# Get the total number of testers
11910750Sandreas.hansson@arm.comdef numtesters(cachespec, testerspec):
12010750Sandreas.hansson@arm.com     # Determine the tester multiplier for each level as the
12110750Sandreas.hansson@arm.com     # elements are per subsystem and it fans out
12210750Sandreas.hansson@arm.com     multiplier = [1]
12310750Sandreas.hansson@arm.com     for c in cachespec:
12410750Sandreas.hansson@arm.com          multiplier.append(multiplier[-1] * c)
12510750Sandreas.hansson@arm.com
12610750Sandreas.hansson@arm.com     total = 0
12710750Sandreas.hansson@arm.com     for t, m in zip(testerspec, multiplier):
12810750Sandreas.hansson@arm.com          total += t * m
12910750Sandreas.hansson@arm.com
13010750Sandreas.hansson@arm.com     return total
13110750Sandreas.hansson@arm.com
1324626Sstever@eecs.umich.edublock_size = 64
1334626Sstever@eecs.umich.edu
13410705Sandreas.hansson@arm.com# Start by parsing the command line options and do some basic sanity
13510690Sandreas.hansson@arm.com# checking
13610750Sandreas.hansson@arm.comif options.random:
13710750Sandreas.hansson@arm.com     # Generate a tree with a valid number of testers
13810750Sandreas.hansson@arm.com     while True:
13910750Sandreas.hansson@arm.com          tree_depth = random.randint(1, 4)
14010750Sandreas.hansson@arm.com          cachespec = [random.randint(1, 3) for i in range(tree_depth)]
14110750Sandreas.hansson@arm.com          testerspec = [random.randint(1, 3) for i in range(tree_depth + 1)]
14210750Sandreas.hansson@arm.com          if numtesters(cachespec, testerspec) < block_size:
14310750Sandreas.hansson@arm.com               break
1443354Srdreslin@umich.edu
14512564Sgabeblack@google.com     print("Generated random tree -c", ':'.join(map(str, cachespec)),
14612564Sgabeblack@google.com         "-t", ':'.join(map(str, testerspec)))
14710750Sandreas.hansson@arm.comelse:
14810750Sandreas.hansson@arm.com     try:
14910750Sandreas.hansson@arm.com          cachespec = [int(x) for x in options.caches.split(':')]
15010750Sandreas.hansson@arm.com          testerspec = [int(x) for x in options.testers.split(':')]
15110750Sandreas.hansson@arm.com     except:
15212564Sgabeblack@google.com          print("Error: Unable to parse caches or testers option")
15310690Sandreas.hansson@arm.com          sys.exit(1)
15410690Sandreas.hansson@arm.com
15510750Sandreas.hansson@arm.com     if len(cachespec) < 1:
15612564Sgabeblack@google.com          print("Error: Must have at least one level of caches")
15710690Sandreas.hansson@arm.com          sys.exit(1)
15810690Sandreas.hansson@arm.com
15910750Sandreas.hansson@arm.com     if len(cachespec) != len(testerspec) - 1:
16012564Sgabeblack@google.com          print("Error: Testers must have one element more than caches")
16110750Sandreas.hansson@arm.com          sys.exit(1)
16210690Sandreas.hansson@arm.com
16310750Sandreas.hansson@arm.com     if testerspec[-1] == 0:
16412564Sgabeblack@google.com          print("Error: Must have testers at the uppermost level")
16510750Sandreas.hansson@arm.com          sys.exit(1)
16610690Sandreas.hansson@arm.com
16710750Sandreas.hansson@arm.com     for t in testerspec:
16810750Sandreas.hansson@arm.com          if t < 0:
16912564Sgabeblack@google.com               print("Error: Cannot have a negative number of testers")
17010750Sandreas.hansson@arm.com               sys.exit(1)
17110750Sandreas.hansson@arm.com
17210750Sandreas.hansson@arm.com     for c in cachespec:
17310750Sandreas.hansson@arm.com          if c < 1:
17412564Sgabeblack@google.com               print("Error: Must have 1 or more caches at each level")
17510750Sandreas.hansson@arm.com               sys.exit(1)
17610750Sandreas.hansson@arm.com
17710750Sandreas.hansson@arm.com     if numtesters(cachespec, testerspec) > block_size:
17812564Sgabeblack@google.com          print("Error: Limited to %s testers because of false sharing"
17912564Sgabeblack@google.com              % (block_size))
18010750Sandreas.hansson@arm.com          sys.exit(1)
1813354Srdreslin@umich.edu
18210690Sandreas.hansson@arm.com# Define a prototype L1 cache that we scale for all successive levels
18311053Sandreas.hansson@arm.comproto_l1 = Cache(size = '32kB', assoc = 4,
18411722Ssophiane.senni@gmail.com                 tag_latency = 1, data_latency = 1, response_latency = 1,
18511200Sandreas.hansson@arm.com                 tgts_per_mshr = 8, clusivity = 'mostly_incl',
18611200Sandreas.hansson@arm.com                 writeback_clean = True)
1874890Sstever@eecs.umich.edu
1884890Sstever@eecs.umich.eduif options.blocking:
1894890Sstever@eecs.umich.edu     proto_l1.mshrs = 1
1904890Sstever@eecs.umich.eduelse:
1917656Ssteve.reinhardt@amd.com     proto_l1.mshrs = 4
1924890Sstever@eecs.umich.edu
19310690Sandreas.hansson@arm.comcache_proto = [proto_l1]
1944890Sstever@eecs.umich.edu
19510690Sandreas.hansson@arm.com# Now add additional cache levels (if any) by scaling L1 params, the
19610690Sandreas.hansson@arm.com# first element is Ln, and the last element L1
19710690Sandreas.hansson@arm.comfor scale in cachespec[:-1]:
19810690Sandreas.hansson@arm.com     # Clone previous level and update params
19910690Sandreas.hansson@arm.com     prev = cache_proto[0]
2004890Sstever@eecs.umich.edu     next = prev()
2017656Ssteve.reinhardt@amd.com     next.size = prev.size * scale
20211722Ssophiane.senni@gmail.com     next.tag_latency = prev.tag_latency * 10
20311722Ssophiane.senni@gmail.com     next.data_latency = prev.data_latency * 10
20410270Sradhika.jagtap@ARM.com     next.response_latency = prev.response_latency * 10
2057656Ssteve.reinhardt@amd.com     next.assoc = prev.assoc * scale
2067656Ssteve.reinhardt@amd.com     next.mshrs = prev.mshrs * scale
20711198Sandreas.hansson@arm.com
20811198Sandreas.hansson@arm.com     # Swap the inclusivity/exclusivity at each level. L2 is mostly
20911198Sandreas.hansson@arm.com     # exclusive with respect to L1, L3 mostly inclusive, L4 mostly
21011198Sandreas.hansson@arm.com     # exclusive etc.
21111200Sandreas.hansson@arm.com     next.writeback_clean = not prev.writeback_clean
21211198Sandreas.hansson@arm.com     if (prev.clusivity.value == 'mostly_incl'):
21311198Sandreas.hansson@arm.com          next.clusivity = 'mostly_excl'
21411198Sandreas.hansson@arm.com     else:
21511198Sandreas.hansson@arm.com          next.clusivity = 'mostly_incl'
21611198Sandreas.hansson@arm.com
21710690Sandreas.hansson@arm.com     cache_proto.insert(0, next)
2184467Sstever@eecs.umich.edu
21910690Sandreas.hansson@arm.com# Make a prototype for the tester to be used throughout
22010690Sandreas.hansson@arm.comproto_tester = MemTest(max_loads = options.maxloads,
22110690Sandreas.hansson@arm.com                       percent_functional = options.functional,
22210690Sandreas.hansson@arm.com                       percent_uncacheable = options.uncacheable,
22310690Sandreas.hansson@arm.com                       progress_interval = options.progress)
22410690Sandreas.hansson@arm.com
22510690Sandreas.hansson@arm.com# Set up the system along with a simple memory and reference memory
22610690Sandreas.hansson@arm.comsystem = System(physmem = SimpleMemory(),
2279815SAndreas Hansson <andreas.hansson>                cache_line_size = block_size)
2289928SAli.Saidi@ARM.com
2299928SAli.Saidi@ARM.comsystem.voltage_domain = VoltageDomain(voltage = '1V')
2309928SAli.Saidi@ARM.com
2319928SAli.Saidi@ARM.comsystem.clk_domain = SrcClockDomain(clock =  options.sys_clock,
2329928SAli.Saidi@ARM.com                        voltage_domain = system.voltage_domain)
2333354Srdreslin@umich.edu
23410690Sandreas.hansson@arm.com# For each level, track the next subsys index to use
23510690Sandreas.hansson@arm.comnext_subsys_index = [0] * (len(cachespec) + 1)
23610690Sandreas.hansson@arm.com
23710690Sandreas.hansson@arm.com# Recursive function to create a sub-tree of the cache and tester
23810690Sandreas.hansson@arm.com# hierarchy
23910690Sandreas.hansson@arm.comdef make_cache_level(ncaches, prototypes, level, next_cache):
24010690Sandreas.hansson@arm.com     global next_subsys_index, proto_l1, testerspec, proto_tester
24110690Sandreas.hansson@arm.com
24210690Sandreas.hansson@arm.com     index = next_subsys_index[level]
24310690Sandreas.hansson@arm.com     next_subsys_index[level] += 1
24410690Sandreas.hansson@arm.com
24510690Sandreas.hansson@arm.com     # Create a subsystem to contain the crossbar and caches, and
24610690Sandreas.hansson@arm.com     # any testers
24710690Sandreas.hansson@arm.com     subsys = SubSystem()
24810690Sandreas.hansson@arm.com     setattr(system, 'l%dsubsys%d' % (level, index), subsys)
24910690Sandreas.hansson@arm.com
25010690Sandreas.hansson@arm.com     # The levels are indexing backwards through the list
25110690Sandreas.hansson@arm.com     ntesters = testerspec[len(cachespec) - level]
25210690Sandreas.hansson@arm.com
25310690Sandreas.hansson@arm.com     # Scale the progress threshold as testers higher up in the tree
25410690Sandreas.hansson@arm.com     # (smaller level) get a smaller portion of the overall bandwidth,
25510690Sandreas.hansson@arm.com     # and also make the interval of packet injection longer for the
25610690Sandreas.hansson@arm.com     # testers closer to the memory (larger level) to prevent them
25710690Sandreas.hansson@arm.com     # hogging all the bandwidth
25810750Sandreas.hansson@arm.com     limit = (len(cachespec) - level + 1) * 100000000
25910690Sandreas.hansson@arm.com     testers = [proto_tester(interval = 10 * (level * level + 1),
26010690Sandreas.hansson@arm.com                             progress_check = limit) \
26113731Sandreas.sandberg@arm.com                     for i in range(ntesters)]
26210690Sandreas.hansson@arm.com     if ntesters:
26310690Sandreas.hansson@arm.com          subsys.tester = testers
26410690Sandreas.hansson@arm.com
26510690Sandreas.hansson@arm.com     if level != 0:
26610690Sandreas.hansson@arm.com          # Create a crossbar and add it to the subsystem, note that
26710690Sandreas.hansson@arm.com          # we do this even with a single element on this level
26810720Sandreas.hansson@arm.com          xbar = L2XBar()
26910690Sandreas.hansson@arm.com          subsys.xbar = xbar
27010690Sandreas.hansson@arm.com          if next_cache:
27110690Sandreas.hansson@arm.com               xbar.master = next_cache.cpu_side
27210690Sandreas.hansson@arm.com
27310690Sandreas.hansson@arm.com          # Create and connect the caches, both the ones fanning out
27410690Sandreas.hansson@arm.com          # to create the tree, and the ones used to connect testers
27510690Sandreas.hansson@arm.com          # on this level
27613731Sandreas.sandberg@arm.com          tree_caches = [prototypes[0]() for i in range(ncaches[0])]
27713731Sandreas.sandberg@arm.com          tester_caches = [proto_l1() for i in range(ntesters)]
27810690Sandreas.hansson@arm.com
27910690Sandreas.hansson@arm.com          subsys.cache = tester_caches + tree_caches
28010690Sandreas.hansson@arm.com          for cache in tree_caches:
28110690Sandreas.hansson@arm.com               cache.mem_side = xbar.slave
28210690Sandreas.hansson@arm.com               make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
28310690Sandreas.hansson@arm.com          for tester, cache in zip(testers, tester_caches):
28410690Sandreas.hansson@arm.com               tester.port = cache.cpu_side
28510690Sandreas.hansson@arm.com               cache.mem_side = xbar.slave
28610690Sandreas.hansson@arm.com     else:
28710690Sandreas.hansson@arm.com          if not next_cache:
28812564Sgabeblack@google.com               print("Error: No next-level cache at top level")
28910690Sandreas.hansson@arm.com               sys.exit(1)
29010690Sandreas.hansson@arm.com
29110690Sandreas.hansson@arm.com          if ntesters > 1:
29210690Sandreas.hansson@arm.com               # Create a crossbar and add it to the subsystem
29310720Sandreas.hansson@arm.com               xbar = L2XBar()
29410690Sandreas.hansson@arm.com               subsys.xbar = xbar
29510690Sandreas.hansson@arm.com               xbar.master = next_cache.cpu_side
29610690Sandreas.hansson@arm.com               for tester in testers:
29710690Sandreas.hansson@arm.com                    tester.port = xbar.slave
2988847Sandreas.hansson@arm.com          else:
29910690Sandreas.hansson@arm.com               # Single tester
30010690Sandreas.hansson@arm.com               testers[0].port = next_cache.cpu_side
3013354Srdreslin@umich.edu
30210690Sandreas.hansson@arm.com# Top level call to create the cache hierarchy, bottom up
30310690Sandreas.hansson@arm.commake_cache_level(cachespec, cache_proto, len(cachespec), None)
3043354Srdreslin@umich.edu
30512726Snikos.nikoleris@arm.com# Connect the lowest level crossbar to the last-level cache and memory
30612726Snikos.nikoleris@arm.com# controller
30710690Sandreas.hansson@arm.comlast_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
30811334Sandreas.hansson@arm.comlast_subsys.xbar.point_of_coherency = True
30912726Snikos.nikoleris@arm.comif options.noncoherent_cache:
31012726Snikos.nikoleris@arm.com     system.llc = NoncoherentCache(size = '16MB', assoc = 16, tag_latency = 10,
31112726Snikos.nikoleris@arm.com                                   data_latency = 10, sequential_access = True,
31212726Snikos.nikoleris@arm.com                                   response_latency = 20, tgts_per_mshr = 8,
31312726Snikos.nikoleris@arm.com                                   mshrs = 64)
31412726Snikos.nikoleris@arm.com     last_subsys.xbar.master = system.llc.cpu_side
31512726Snikos.nikoleris@arm.com     system.llc.mem_side = system.physmem.port
31612726Snikos.nikoleris@arm.comelse:
31712726Snikos.nikoleris@arm.com     last_subsys.xbar.master = system.physmem.port
3183354Srdreslin@umich.edu
31910690Sandreas.hansson@arm.comroot = Root(full_system = False, system = system)
3204626Sstever@eecs.umich.eduif options.atomic:
3214626Sstever@eecs.umich.edu    root.system.mem_mode = 'atomic'
3224626Sstever@eecs.umich.eduelse:
3233354Srdreslin@umich.edu    root.system.mem_mode = 'timing'
3243354Srdreslin@umich.edu
3258847Sandreas.hansson@arm.com# The system port is never used in the tester so merely connect it
3268847Sandreas.hansson@arm.com# to avoid problems
32710690Sandreas.hansson@arm.comroot.system.system_port = last_subsys.xbar.slave
3288847Sandreas.hansson@arm.com
32910690Sandreas.hansson@arm.com# Instantiate configuration
3307525Ssteve.reinhardt@amd.comm5.instantiate()
3313354Srdreslin@umich.edu
33210690Sandreas.hansson@arm.com# Simulate until program terminates
3334626Sstever@eecs.umich.eduexit_event = m5.simulate(options.maxtick)
3343354Srdreslin@umich.edu
33512564Sgabeblack@google.comprint('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause())
336