1# Copyright (c) 2012 ARM Limited
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3#
4# The license below extends only to copyright in the software and shall
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24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35#
36# Authors: Andreas Hansson
37
38import m5
39from m5.objects import *
40
41import argparse
42
43parser = argparse.ArgumentParser(description='Simple memory tester')
44parser.add_argument('--bandwidth', default=None)
45parser.add_argument('--latency', default=None)
46parser.add_argument('--latency_var', default=None)
47
48args = parser.parse_args()
49
50# even if this is only a traffic generator, call it cpu to make sure
51# the scripts are happy
52try:
53    cpu = TrafficGen(
54        config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
55                             "tgen-simple-mem.cfg"))
56except NameError:
57    m5.fatal("protobuf required for simple memory test")
58
59class MyMem(SimpleMemory):
60    if args.bandwidth:
61        bandwidth = args.bandwidth
62    if args.latency:
63        latency = args.latency
64    if args.latency_var:
65        latency_var = args.latency_var
66
67# system simulated
68system = System(cpu = cpu, physmem = MyMem(),
69                membus = IOXBar(width = 16),
70                clk_domain = SrcClockDomain(clock = '1GHz',
71                                            voltage_domain =
72                                            VoltageDomain()))
73
74# add a communication monitor, and also trace all the packets and
75# calculate and verify stack distance
76system.monitor = CommMonitor()
77system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
78system.monitor.stackdist = StackDistProbe(verify = True)
79
80# connect the traffic generator to the bus via a communication monitor
81system.cpu.port = system.monitor.slave
82system.monitor.master = system.membus.slave
83
84# connect the system port even if it is not used in this example
85system.system_port = system.membus.slave
86
87# connect memory to the membus
88system.physmem.port = system.membus.master
89
90# -----------------------
91# run simulation
92# -----------------------
93
94root = Root(full_system = False, system = system)
95root.system.mem_mode = 'timing'
96
97m5.instantiate()
98exit_event = m5.simulate(100000000000)
99if exit_event.getCause() != "simulate() limit reached":
100    exit(1)
101