/gem5/util/tlm/examples/ |
H A D | tlm_elastic_slave_with_l2.py | 74 # Create a system with a Crossbar and an Elastic Trace Player as CPU: 77 system = System(cpu=TraceCPU(cpu_id=0), variable 83 system.voltage_domain = VoltageDomain() 85 # Create a source clock for the system. This is used as the clock period for 87 system.clk_domain = SrcClockDomain(clock = '1GHz', 88 voltage_domain = system.voltage_domain) 91 system.cpu_voltage_domain = VoltageDomain() 95 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', 96 voltage_domain = system.cpu_voltage_domain) 99 system [all...] |
/gem5/util/tlm/conf/ |
H A D | tlm_slave.py | 55 # Create a system with a Crossbar and a TrafficGenerator as CPU: 56 system = System() variable 57 system.membus = IOXBar(width = 16) 58 system.physmem = SimpleMemory() # This must be instanciated, even if not needed 59 system.cpu = TrafficGen(config_file = "conf/tgen.cfg") 60 system.clk_domain = SrcClockDomain(clock = '1.5GHz', 64 system.tlm = ExternalSlave() 65 system.tlm.addr_ranges = [AddrRange('512MB')] 66 system.tlm.port_type = "tlm_slave" 67 system [all...] |
H A D | tlm_elastic_slave.py | 67 # Create a system with a Crossbar and an Elastic Trace Player as CPU: 70 system = System(cpu=TraceCPU(cpu_id=0), variable 76 system.voltage_domain = VoltageDomain() 78 # Create a source clock for the system. This is used as the clock period for 80 system.clk_domain = SrcClockDomain(clock = '1GHz', 81 voltage_domain = system.voltage_domain) 84 system.cpu_voltage_domain = VoltageDomain() 88 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', 89 voltage_domain = system.cpu_voltage_domain) 92 system [all...] |
H A D | tlm_master.py | 54 # Create a system with a Crossbar and a simple Memory: 55 system = System() variable 56 system.membus = IOXBar(width = 16) 57 system.physmem = SimpleMemory(range = AddrRange('512MB')) 58 system.clk_domain = SrcClockDomain(clock = '1.5GHz', 62 system.tlm = ExternalMaster() 63 system.tlm.port_type = "tlm_master" 64 system.tlm.port_data = "transactor" 67 system.system_port = system [all...] |
/gem5/configs/learning_gem5/part3/ |
H A D | ruby_test.py | 30 """ This file creates a system with Ruby caches and runs the ruby random tester 47 # create the system we are going to simulate 48 system = System() variable 50 # Set the clock fequency of the system (and all of its children) 51 system.clk_domain = SrcClockDomain() 52 system.clk_domain.clock = '1GHz' 53 system.clk_domain.voltage_domain = VoltageDomain() 55 # Set up the system 56 system.mem_mode = 'timing' # Use timing accesses 57 system [all...] |
H A D | simple_ruby.py | 30 """ This file creates a system with Ruby caches and executes 'threads', a 56 # create the system we are going to simulate 57 system = System() variable 59 # Set the clock fequency of the system (and all of its children) 60 system.clk_domain = SrcClockDomain() 61 system.clk_domain.clock = '1GHz' 62 system.clk_domain.voltage_domain = VoltageDomain() 64 # Set up the system 65 system.mem_mode = 'timing' # Use timing accesses 66 system [all...] |
/gem5/configs/learning_gem5/part2/ |
H A D | simple_cache.py | 30 """ This file creates a barebones system and executes 'hello', a simple Hello 44 # create the system we are going to simulate 45 system = System() variable 47 # Set the clock fequency of the system (and all of its children) 48 system.clk_domain = SrcClockDomain() 49 system.clk_domain.clock = '1GHz' 50 system.clk_domain.voltage_domain = VoltageDomain() 52 # Set up the system 53 system.mem_mode = 'timing' # Use timing accesses 54 system [all...] |
H A D | simple_memobj.py | 30 """ This file creates a barebones system and executes 'hello', a simple Hello 44 # create the system we are going to simulate 45 system = System() variable 47 # Set the clock fequency of the system (and all of its children) 48 system.clk_domain = SrcClockDomain() 49 system.clk_domain.clock = '1GHz' 50 system.clk_domain.voltage_domain = VoltageDomain() 52 # Set up the system 53 system.mem_mode = 'timing' # Use timing accesses 54 system [all...] |
/gem5/tests/configs/ |
H A D | t1000-simple-atomic.py | 35 system = FSConfig.makeSparcSystem('atomic') variable 39 system.voltage_domain = VoltageDomain() 40 system.clk_domain = SrcClockDomain(clock = '1GHz', 41 voltage_domain = system.voltage_domain) 42 system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', 43 voltage_domain = system.voltage_domain) 44 cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) 45 system.cpu = cpu 48 cpu.connectAllPorts(system.membus) 52 system [all...] |
H A D | tgen-simple-mem.py | 51 # system simulated 52 system = System(cpu = cpu, physmem = SimpleMemory(), variable 60 system.monitor = CommMonitor() 61 system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz") 62 system.monitor.stackdist = StackDistProbe(verify = True) 65 system.cpu.port = system.monitor.slave 66 system.monitor.master = system.membus.slave 68 # connect the system por [all...] |
H A D | memtest.py | 38 # system simulated 39 system = System(cpu = cpus, variable 43 system.voltage_domain = VoltageDomain() 44 system.clk_domain = SrcClockDomain(clock = '1GHz', 45 voltage_domain = system.voltage_domain) 49 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 50 voltage_domain = system.voltage_domain) 52 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) 53 system [all...] |
H A D | memtest-filter.py | 38 # system simulated 39 system = System(cpu = cpus, variable 43 system.voltage_domain = VoltageDomain() 44 system.clk_domain = SrcClockDomain(clock = '1GHz', 45 voltage_domain = system.voltage_domain) 49 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 50 voltage_domain = system.voltage_domain) 52 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain, 54 system [all...] |
H A D | tgen-dram-ctrl.py | 51 # system simulated 52 system = System(cpu = cpu, physmem = DDR3_1600_8x8(), variable 59 system.monitor = CommMonitor() 62 system.cpu.port = system.monitor.slave 63 system.monitor.master = system.membus.slave 65 # connect the system port even if it is not used in this example 66 system.system_port = system [all...] |
H A D | o3-timing-ruby.py | 37 system = System(cpu = cpu, variable 45 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 47 system.physmem.port = system.membus.master 50 cpu.connectAllPorts(system.membus) 52 # Connect the system port for loading of binaries etc 53 system.system_port = system.membus.slave 55 root = Root(full_system = False, system = system) [all...] |
H A D | o3-timing-mp-ruby.py | 38 # system simulated 39 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(), variable 45 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') 50 cpu.connectAllPorts(system.membus) 52 cpu.clk_domain = system.cpu_clk_domain 55 system.physmem.port = system.membus.master 57 # Connect the system port for loading of binaries etc 58 system.system_port = system [all...] |
H A D | simple-atomic-mp-ruby.py | 38 # system simulated 39 system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(), variable 44 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 48 cpu.connectAllPorts(system.membus) 50 cpu.clk_domain = system.cpu_clk_domain 53 system.physmem.port = system.membus.master 55 # Connect the system port for loading of binaries etc 56 system.system_port = system [all...] |
/gem5/configs/learning_gem5/part1/ |
H A D | two_level.py | 30 """ This file creates a single CPU and a two-level cache system. 83 # create the system we are going to simulate 84 system = System() variable 86 # Set the clock fequency of the system (and all of its children) 87 system.clk_domain = SrcClockDomain() 88 system.clk_domain.clock = '1GHz' 89 system.clk_domain.voltage_domain = VoltageDomain() 91 # Set up the system 92 system.mem_mode = 'timing' # Use timing accesses 93 system [all...] |
H A D | simple.py | 30 """ This file creates a barebones system and executes 'hello', a simple Hello 49 # create the system we are going to simulate 50 system = System() variable 52 # Set the clock fequency of the system (and all of its children) 53 system.clk_domain = SrcClockDomain() 54 system.clk_domain.clock = '1GHz' 55 system.clk_domain.voltage_domain = VoltageDomain() 57 # Set up the system 58 system.mem_mode = 'timing' # Use timing accesses 59 system [all...] |
/gem5/tests/gem5/memory/ |
H A D | memtest-run.py | 39 # system simulated 40 system = System(cpu = cpus, variable 44 system.voltage_domain = VoltageDomain() 45 system.clk_domain = SrcClockDomain(clock = '1GHz', 46 voltage_domain = system.voltage_domain) 50 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 51 voltage_domain = system.voltage_domain) 53 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) 54 system [all...] |
/gem5/tests/gem5/cpu_tests/ |
H A D | run.py | 122 system = System() variable 124 system.clk_domain = SrcClockDomain() 125 system.clk_domain.clock = '1GHz' 126 system.clk_domain.voltage_domain = VoltageDomain() 129 system.mem_mode = 'timing' 131 system.mem_ranges = [AddrRange('512MB')] 133 system.cpu = valid_cpu[args.cpu]() 136 system.membus = SystemXBar() 137 system.cpu.icache_port = system [all...] |
/gem5/tests/long/fs/10.linux-boot/ |
H A D | test.py | 29 root.system.readfile = os.path.join(tests_root, 'halt.sh')
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/gem5/tests/long/fs/80.solaris-boot/ |
H A D | test.py | 29 root.system.readfile = os.path.join(tests_root, 'halt.sh')
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/gem5/tests/quick/fs/10.linux-boot/ |
H A D | test.py | 29 root.system.readfile = os.path.join(tests_root, 'halt.sh')
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/gem5/tests/quick/se/00.hello/ |
H A D | test.py | 29 root.system.cpu[0].workload = Process(cmd = 'hello', 31 if root.system.cpu[0].checker != NULL: 32 root.system.cpu[0].checker.workload = root.system.cpu[0].workload
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/gem5/tests/quick/se/02.insttest/ |
H A D | test.py | 29 root.system.cpu[0].workload = Process(cmd = 'insttest',
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