learning_gem5/part1/two_level.py

30 """ This file creates a single CPU and a two-level cache system.
83 # create the system we are going to simulate
84 system = System()
86 # Set the clock fequency of the system (and all of its children)
87 system.clk_domain = SrcClockDomain()
88 system.clk_domain.clock = '1GHz'
89 system.clk_domain.voltage_domain = VoltageDomain()
91 # Set up the system
92 system.mem_mode = 'timing'               # Use timing accesses
93 system.mem_ranges = [AddrRange('512MB')] # Create an address range
96 system.cpu = TimingSimpleCPU()
99 system.cpu.icache = L1ICache(opts)
100 system.cpu.dcache = L1DCache(opts)
103 system.cpu.icache.connectCPU(system.cpu)
104 system.cpu.dcache.connectCPU(system.cpu)
107 system.l2bus = L2XBar()
110 system.cpu.icache.connectBus(system.l2bus)
111 system.cpu.dcache.connectBus(system.l2bus)
114 system.l2cache = L2Cache(opts)
115 system.l2cache.connectCPUSideBus(system.l2bus)
118 system.membus = SystemXBar()
121 system.l2cache.connectMemSideBus(system.membus)
124 system.cpu.createInterruptController()
129     system.cpu.interrupts[0].pio = system.membus.master
130     system.cpu.interrupts[0].int_master = system.membus.slave
131     system.cpu.interrupts[0].int_slave = system.membus.master
133 # Connect the system up to the membus
134 system.system_port = system.membus.slave
137 system.mem_ctrl = DDR3_1600_8x8()
138 system.mem_ctrl.range = system.mem_ranges[0]
139 system.mem_ctrl.port = system.membus.master
147 system.cpu.workload = process
148 system.cpu.createThreads()
151 root = Root(full_system = False, system = system)