112338Sjason@lowepower.com# -*- coding: utf-8 -*- 212338Sjason@lowepower.com# Copyright (c) 2017 Jason Lowe-Power 312338Sjason@lowepower.com# All rights reserved. 412338Sjason@lowepower.com# 512338Sjason@lowepower.com# Redistribution and use in source and binary forms, with or without 612338Sjason@lowepower.com# modification, are permitted provided that the following conditions are 712338Sjason@lowepower.com# met: redistributions of source code must retain the above copyright 812338Sjason@lowepower.com# notice, this list of conditions and the following disclaimer; 912338Sjason@lowepower.com# redistributions in binary form must reproduce the above copyright 1012338Sjason@lowepower.com# notice, this list of conditions and the following disclaimer in the 1112338Sjason@lowepower.com# documentation and/or other materials provided with the distribution; 1212338Sjason@lowepower.com# neither the name of the copyright holders nor the names of its 1312338Sjason@lowepower.com# contributors may be used to endorse or promote products derived from 1412338Sjason@lowepower.com# this software without specific prior written permission. 1512338Sjason@lowepower.com# 1612338Sjason@lowepower.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712338Sjason@lowepower.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812338Sjason@lowepower.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912338Sjason@lowepower.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012338Sjason@lowepower.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112338Sjason@lowepower.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212338Sjason@lowepower.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312338Sjason@lowepower.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412338Sjason@lowepower.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512338Sjason@lowepower.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612338Sjason@lowepower.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712338Sjason@lowepower.com# 2812338Sjason@lowepower.com# Authors: Jason Lowe-Power 2912338Sjason@lowepower.com 3012338Sjason@lowepower.com""" This file creates a barebones system and executes 'hello', a simple Hello 3112338Sjason@lowepower.comWorld application. Adds a simple memobj between the CPU and the membus. 3212338Sjason@lowepower.com 3312338Sjason@lowepower.comThis config file assumes that the x86 ISA was built. 3412338Sjason@lowepower.com""" 3512338Sjason@lowepower.com 3612564Sgabeblack@google.comfrom __future__ import print_function 3713774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 3812564Sgabeblack@google.com 3912338Sjason@lowepower.com# import the m5 (gem5) library created when gem5 is built 4012338Sjason@lowepower.comimport m5 4112338Sjason@lowepower.com# import all of the SimObjects 4212338Sjason@lowepower.comfrom m5.objects import * 4312338Sjason@lowepower.com 4412338Sjason@lowepower.com# create the system we are going to simulate 4512338Sjason@lowepower.comsystem = System() 4612338Sjason@lowepower.com 4712338Sjason@lowepower.com# Set the clock fequency of the system (and all of its children) 4812338Sjason@lowepower.comsystem.clk_domain = SrcClockDomain() 4912338Sjason@lowepower.comsystem.clk_domain.clock = '1GHz' 5012338Sjason@lowepower.comsystem.clk_domain.voltage_domain = VoltageDomain() 5112338Sjason@lowepower.com 5212338Sjason@lowepower.com# Set up the system 5312338Sjason@lowepower.comsystem.mem_mode = 'timing' # Use timing accesses 5412338Sjason@lowepower.comsystem.mem_ranges = [AddrRange('512MB')] # Create an address range 5512338Sjason@lowepower.com 5612338Sjason@lowepower.com# Create a simple CPU 5712338Sjason@lowepower.comsystem.cpu = TimingSimpleCPU() 5812338Sjason@lowepower.com 5912338Sjason@lowepower.com# Create the simple memory object 6012338Sjason@lowepower.comsystem.memobj = SimpleMemobj() 6112338Sjason@lowepower.com 6212338Sjason@lowepower.com# Hook the CPU ports up to the cache 6312338Sjason@lowepower.comsystem.cpu.icache_port = system.memobj.inst_port 6412338Sjason@lowepower.comsystem.cpu.dcache_port = system.memobj.data_port 6512338Sjason@lowepower.com 6612338Sjason@lowepower.com# Create a memory bus, a coherent crossbar, in this case 6712338Sjason@lowepower.comsystem.membus = SystemXBar() 6812338Sjason@lowepower.com 6912338Sjason@lowepower.com# Connect the memobj 7012338Sjason@lowepower.comsystem.memobj.mem_side = system.membus.slave 7112338Sjason@lowepower.com 7212338Sjason@lowepower.com# create the interrupt controller for the CPU and connect to the membus 7312338Sjason@lowepower.comsystem.cpu.createInterruptController() 7412338Sjason@lowepower.comsystem.cpu.interrupts[0].pio = system.membus.master 7512338Sjason@lowepower.comsystem.cpu.interrupts[0].int_master = system.membus.slave 7612338Sjason@lowepower.comsystem.cpu.interrupts[0].int_slave = system.membus.master 7712338Sjason@lowepower.com 7812338Sjason@lowepower.com# Create a DDR3 memory controller and connect it to the membus 7912338Sjason@lowepower.comsystem.mem_ctrl = DDR3_1600_8x8() 8012338Sjason@lowepower.comsystem.mem_ctrl.range = system.mem_ranges[0] 8112338Sjason@lowepower.comsystem.mem_ctrl.port = system.membus.master 8212338Sjason@lowepower.com 8312338Sjason@lowepower.com# Connect the system up to the membus 8412338Sjason@lowepower.comsystem.system_port = system.membus.slave 8512338Sjason@lowepower.com 8612338Sjason@lowepower.com# Create a process for a simple "Hello World" application 8712338Sjason@lowepower.comprocess = Process() 8812338Sjason@lowepower.com# Set the command 8913839Sjason@lowepower.com# grab the specific path to the binary 9013839Sjason@lowepower.comthispath = os.path.dirname(os.path.realpath(__file__)) 9113839Sjason@lowepower.combinpath = os.path.join(thispath, '../../../', 9213839Sjason@lowepower.com 'tests/test-progs/hello/bin/x86/linux/hello') 9312338Sjason@lowepower.com# cmd is a list which begins with the executable (like argv) 9413839Sjason@lowepower.comprocess.cmd = [binpath] 9512338Sjason@lowepower.com# Set the cpu to use the process as its workload and create thread contexts 9612338Sjason@lowepower.comsystem.cpu.workload = process 9712338Sjason@lowepower.comsystem.cpu.createThreads() 9812338Sjason@lowepower.com 9912338Sjason@lowepower.com# set up the root SimObject and start the simulation 10012338Sjason@lowepower.comroot = Root(full_system = False, system = system) 10112338Sjason@lowepower.com# instantiate all of the objects we've created above 10212338Sjason@lowepower.comm5.instantiate() 10312338Sjason@lowepower.com 10412564Sgabeblack@google.comprint("Beginning simulation!") 10512338Sjason@lowepower.comexit_event = m5.simulate() 10612564Sgabeblack@google.comprint('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) 107