Lines Matching refs:system
30 """ This file creates a barebones system and executes 'hello', a simple Hello
44 # create the system we are going to simulate
45 system = System()
47 # Set the clock fequency of the system (and all of its children)
48 system.clk_domain = SrcClockDomain()
49 system.clk_domain.clock = '1GHz'
50 system.clk_domain.voltage_domain = VoltageDomain()
52 # Set up the system
53 system.mem_mode = 'timing' # Use timing accesses
54 system.mem_ranges = [AddrRange('512MB')] # Create an address range
57 system.cpu = TimingSimpleCPU()
60 system.memobj = SimpleMemobj()
63 system.cpu.icache_port = system.memobj.inst_port
64 system.cpu.dcache_port = system.memobj.data_port
67 system.membus = SystemXBar()
70 system.memobj.mem_side = system.membus.slave
73 system.cpu.createInterruptController()
74 system.cpu.interrupts[0].pio = system.membus.master
75 system.cpu.interrupts[0].int_master = system.membus.slave
76 system.cpu.interrupts[0].int_slave = system.membus.master
79 system.mem_ctrl = DDR3_1600_8x8()
80 system.mem_ctrl.range = system.mem_ranges[0]
81 system.mem_ctrl.port = system.membus.master
83 # Connect the system up to the membus
84 system.system_port = system.membus.slave
96 system.cpu.workload = process
97 system.cpu.createThreads()
100 root = Root(full_system = False, system = system)