1# -*- coding: utf-8 -*-
2# Copyright (c) 2018 The Regents of the University of California
3# All Rights Reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Jason Lowe-Power
29
30import os
31import argparse
32
33import m5
34from m5.objects import *
35
36class L1Cache(Cache):
37    """Simple L1 Cache with default values"""
38
39    assoc = 8
40    tag_latency = 1
41    data_latency = 1
42    response_latency = 1
43    mshrs = 16
44    tgts_per_mshr = 20
45
46    def connectBus(self, bus):
47        """Connect this cache to a memory-side bus"""
48        self.mem_side = bus.slave
49
50    def connectCPU(self, cpu):
51        """Connect this cache's port to a CPU-side port
52           This must be defined in a subclass"""
53        raise NotImplementedError
54
55class L1ICache(L1Cache):
56    """Simple L1 instruction cache with default values"""
57
58    # Set the default size
59    size = '32kB'
60
61    def connectCPU(self, cpu):
62        """Connect this cache's port to a CPU icache port"""
63        self.cpu_side = cpu.icache_port
64
65class L1DCache(L1Cache):
66    """Simple L1 data cache with default values"""
67
68    # Set the default size
69    size = '32kB'
70
71    def connectCPU(self, cpu):
72        """Connect this cache's port to a CPU dcache port"""
73        self.cpu_side = cpu.dcache_port
74
75class L2Cache(Cache):
76    """Simple L2 Cache with default values"""
77
78    # Default parameters
79    size = '512kB'
80    assoc = 16
81    tag_latency = 10
82    data_latency = 10
83    response_latency = 1
84    mshrs = 20
85    tgts_per_mshr = 12
86
87    def connectCPUSideBus(self, bus):
88        self.cpu_side = bus.master
89
90    def connectMemSideBus(self, bus):
91        self.mem_side = bus.slave
92
93
94class MySimpleMemory(SimpleMemory):
95    latency = '1ns'
96
97if buildEnv['TARGET_ISA'] == 'x86':
98  valid_cpu = {'AtomicSimpleCPU': AtomicSimpleCPU,
99               'TimingSimpleCPU': TimingSimpleCPU,
100               'DerivO3CPU': DerivO3CPU
101              }
102else:
103  valid_cpu = {'AtomicSimpleCPU': AtomicSimpleCPU,
104               'TimingSimpleCPU': TimingSimpleCPU,
105               'MinorCPU': MinorCPU,
106               'DerivO3CPU': DerivO3CPU,
107              }
108
109valid_mem = {'SimpleMemory': MySimpleMemory,
110             'DDR3_1600_8x8': DDR3_1600_8x8
111            }
112
113parser = argparse.ArgumentParser()
114parser.add_argument('binary', type = str)
115parser.add_argument('--cpu', choices = valid_cpu.keys(),
116                    default = 'TimingSimpleCPU')
117parser.add_argument('--mem', choices = valid_mem.keys(),
118                    default = 'SimpleMemory')
119
120args = parser.parse_args()
121
122system = System()
123
124system.clk_domain = SrcClockDomain()
125system.clk_domain.clock = '1GHz'
126system.clk_domain.voltage_domain = VoltageDomain()
127
128if args.cpu != "AtomicSimpleCPU":
129        system.mem_mode = 'timing'
130
131system.mem_ranges = [AddrRange('512MB')]
132
133system.cpu = valid_cpu[args.cpu]()
134
135if args.cpu == "AtomicSimpleCPU":
136    system.membus = SystemXBar()
137    system.cpu.icache_port = system.membus.slave
138    system.cpu.dcache_port = system.membus.slave
139else:
140    system.cpu.l1d = L1DCache()
141    system.cpu.l1i = L1ICache()
142    system.l1_to_l2 = L2XBar()
143    system.l2cache = L2Cache()
144    system.membus = SystemXBar()
145    system.cpu.l1d.connectCPU(system.cpu)
146    system.cpu.l1d.connectBus(system.l1_to_l2)
147    system.cpu.l1i.connectCPU(system.cpu)
148    system.cpu.l1i.connectBus(system.l1_to_l2)
149    system.l2cache.connectCPUSideBus(system.l1_to_l2)
150    system.l2cache.connectMemSideBus(system.membus)
151
152system.cpu.createInterruptController()
153if m5.defines.buildEnv['TARGET_ISA'] == "x86":
154    system.cpu.interrupts[0].pio = system.membus.master
155    system.cpu.interrupts[0].int_master = system.membus.slave
156    system.cpu.interrupts[0].int_slave = system.membus.master
157
158system.mem_ctrl = valid_mem[args.mem]()
159system.mem_ctrl.range = system.mem_ranges[0]
160system.mem_ctrl.port = system.membus.master
161system.system_port = system.membus.slave
162
163process = Process()
164process.cmd = [args.binary]
165system.cpu.workload = process
166system.cpu.createThreads()
167
168root = Root(full_system = False, system = system)
169m5.instantiate()
170
171exit_event = m5.simulate()
172
173if exit_event.getCause() != 'exiting with last active thread context':
174    exit(1)
175