/gem5/configs/ruby/ |
H A D | MOESI_hammer.py | 98 # we use system.cpu[0] to set the clk_domain, thereby ensuring 101 clk_domain = system.cpu[0].clk_domain 103 clk_domain = system.cpu[i].clk_domain 111 clk_domain=clk_domain, 115 dcache=l1d_cache,clk_domain=clk_domain, 174 clk_domain [all...] |
H A D | MOESI_CMP_token.py | 99 # we use system.cpu[0] to set the clk_domain, thereby ensuring 102 clk_domain = system.cpu[0].clk_domain 104 clk_domain = system.cpu[i].clk_domain 119 clk_domain=clk_domain, 123 dcache=l1d_cache, clk_domain=clk_domain, 191 clk_domain [all...] |
H A D | MESI_Three_Level.py | 105 # we use system.cpu[0] to set the clk_domain, thereby ensuring 108 clk_domain = system.cpu[0].clk_domain 110 clk_domain = system.cpu[i].clk_domain 115 clk_domain = clk_domain, ruby_system = ruby_system) 119 clk_domain = clk_domain, 202 clk_domain [all...] |
/gem5/configs/learning_gem5/part1/ |
H A D | two_level.py | 87 system.clk_domain = SrcClockDomain() 88 system.clk_domain.clock = '1GHz' 89 system.clk_domain.voltage_domain = VoltageDomain()
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/gem5/tests/configs/ |
H A D | pc-simple-timing-ruby.py | 62 system.clk_domain = SrcClockDomain(clock = '1GHz', 66 system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) 72 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | tgen-simple-mem.py | 54 clk_domain = SrcClockDomain(clock = '1GHz', variable
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H A D | tgen-dram-ctrl.py | 54 clk_domain = SrcClockDomain(clock = '1GHz', variable
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H A D | rubytest-ruby.py | 81 system.clk_domain = SrcClockDomain(clock = '1GHz', 89 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
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H A D | base_config.py | 87 cpus = [ self.cpu_class(clk_domain=cpu_clk_domain, 114 system.toL2Bus = L2XBar(clk_domain=system.cpu_clk_domain) 115 system.l2c = L2Cache(clk_domain=system.cpu_clk_domain, 178 system.ruby.clk_domain = SrcClockDomain( 196 system.clk_domain = SrcClockDomain(clock = '1GHz', 331 cpus = [ cclass(clk_domain = cpu_clk_domain,
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H A D | gpu-randomtest-ruby.py | 98 system.clk_domain = SrcClockDomain(clock = '1GHz', 106 system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
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/gem5/util/tlm/conf/ |
H A D | tlm_master.py | 58 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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H A D | tlm_slave.py | 60 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
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/gem5/src/arch/mips/ |
H A D | MipsSystem.py | 53 boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock[0]
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/gem5/configs/example/ |
H A D | etrace_replay.py | 93 system.clk_domain = SrcClockDomain(clock = options.sys_clock, 108 cpu.clk_domain = system.cpu_clk_domain
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H A D | ruby_mem_test.py | 110 clk_domain = SrcClockDomain(clock = options.sys_clock), variable 132 system.clk_domain = SrcClockDomain(clock = options.sys_clock, 135 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | ruby_direct_test.py | 99 system.clk_domain = SrcClockDomain(clock = options.sys_clock, 109 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | ruby_random_test.py | 109 system.clk_domain = SrcClockDomain(clock = options.sys_clock, 115 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | hmc_hello.py | 58 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
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/gem5/configs/learning_gem5/part3/ |
H A D | test_caches.py | 82 clk_domain = self.clk_domain,
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H A D | msi_caches.py | 88 clk_domain = self.controllers[i].clk_domain, 141 self.clk_domain = cpu.clk_domain
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H A D | ruby_caches_MI_example.py | 88 clk_domain = self.controllers[i].clk_domain, 138 self.clk_domain = cpu.clk_domain
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/gem5/src/sim/ |
H A D | clocked_object.hh | 118 Clocked(ClockDomain &clk_domain) argument 119 : tick(0), cycle(0), clockDomain(clk_domain)
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H A D | clock_domain.cc | 196 ClockDomain(p, p->clk_domain->voltageDomain()), 197 parent(*p->clk_domain),
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/gem5/src/dev/arm/ |
H A D | RealView.py | 367 # clk_domain can only store one clock (i.e. it is not a VectorParam) 418 clock = state.phandle(self.clk_domain.unproxy(self)) 443 clock = state.phandle(self.clk_domain.unproxy(self)) 460 clock = state.phandle(self.clk_domain.unproxy(self)) 568 if hasattr(d, "clk_domain"): 569 d.clk_domain = clkdomain 685 self.gic.clk_domain = clkdomain 686 self.l2x0_fake.clk_domain = clkdomain 688 self.local_cpu_timer.clk_domain = clkdomain 726 self.uart.clk_domain [all...] |
/gem5/tests/gem5/cpu_tests/ |
H A D | run.py | 124 system.clk_domain = SrcClockDomain() 125 system.clk_domain.clock = '1GHz' 126 system.clk_domain.voltage_domain = VoltageDomain()
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