1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology, create_directories
35from Ruby import send_evicts
36from common import FileSystemConfig
37
38#
39# Declare caches used by the protocol
40#
41class L1Cache(RubyCache): pass
42class L2Cache(RubyCache): pass
43#
44# Probe filter is a cache
45#
46class ProbeFilter(RubyCache): pass
47
48def define_options(parser):
49    parser.add_option("--allow-atomic-migration", action="store_true",
50          help="allow migratory sharing for atomic only accessed blocks")
51    parser.add_option("--pf-on", action="store_true",
52          help="Hammer: enable Probe Filter")
53    parser.add_option("--dir-on", action="store_true",
54          help="Hammer: enable Full-bit Directory")
55
56def create_system(options, full_system, system, dma_ports, bootmem,
57                  ruby_system):
58
59    if buildEnv['PROTOCOL'] != 'MOESI_hammer':
60        panic("This script requires the MOESI_hammer protocol to be built.")
61
62    cpu_sequencers = []
63
64    #
65    # The ruby network creation expects the list of nodes in the system to be
66    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
67    # listed before the directory nodes and directory nodes before dma nodes, etc.
68    #
69    l1_cntrl_nodes = []
70    dma_cntrl_nodes = []
71
72    #
73    # Must create the individual controllers before the network to ensure the
74    # controller constructors are called before the network constructor
75    #
76    block_size_bits = int(math.log(options.cacheline_size, 2))
77
78    for i in range(options.num_cpus):
79        #
80        # First create the Ruby objects associated with this cpu
81        #
82        l1i_cache = L1Cache(size = options.l1i_size,
83                            assoc = options.l1i_assoc,
84                            start_index_bit = block_size_bits,
85                            is_icache = True)
86        l1d_cache = L1Cache(size = options.l1d_size,
87                            assoc = options.l1d_assoc,
88                            start_index_bit = block_size_bits)
89        l2_cache = L2Cache(size = options.l2_size,
90                           assoc = options.l2_assoc,
91                           start_index_bit = block_size_bits)
92
93        # the ruby random tester reuses num_cpus to specify the
94        # number of cpu ports connected to the tester object, which
95        # is stored in system.cpu. because there is only ever one
96        # tester object, num_cpus is not necessarily equal to the
97        # size of system.cpu; therefore if len(system.cpu) == 1
98        # we use system.cpu[0] to set the clk_domain, thereby ensuring
99        # we don't index off the end of the cpu list.
100        if len(system.cpu) == 1:
101            clk_domain = system.cpu[0].clk_domain
102        else:
103            clk_domain = system.cpu[i].clk_domain
104
105        l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
106                                      L1Dcache=l1d_cache, L2cache=l2_cache,
107                                      no_mig_atomic=not \
108                                      options.allow_atomic_migration,
109                                      send_evictions=send_evicts(options),
110                                      transitions_per_cycle=options.ports,
111                                      clk_domain=clk_domain,
112                                      ruby_system=ruby_system)
113
114        cpu_seq = RubySequencer(version=i, icache=l1i_cache,
115                                dcache=l1d_cache,clk_domain=clk_domain,
116                                ruby_system=ruby_system)
117
118        l1_cntrl.sequencer = cpu_seq
119        if options.recycle_latency:
120            l1_cntrl.recycle_latency = options.recycle_latency
121
122        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
123
124        # Add controllers and sequencers to the appropriate lists
125        cpu_sequencers.append(cpu_seq)
126        l1_cntrl_nodes.append(l1_cntrl)
127
128        # Connect the L1 controller and the network
129        # Connect the buffers from the controller to network
130        l1_cntrl.requestFromCache = MessageBuffer()
131        l1_cntrl.requestFromCache.master = ruby_system.network.slave
132        l1_cntrl.responseFromCache = MessageBuffer()
133        l1_cntrl.responseFromCache.master = ruby_system.network.slave
134        l1_cntrl.unblockFromCache = MessageBuffer()
135        l1_cntrl.unblockFromCache.master = ruby_system.network.slave
136
137        l1_cntrl.triggerQueue = MessageBuffer()
138
139        # Connect the buffers from the network to the controller
140        l1_cntrl.mandatoryQueue = MessageBuffer()
141        l1_cntrl.forwardToCache = MessageBuffer()
142        l1_cntrl.forwardToCache.slave = ruby_system.network.master
143        l1_cntrl.responseToCache = MessageBuffer()
144        l1_cntrl.responseToCache.slave = ruby_system.network.master
145
146
147    #
148    # determine size and index bits for probe filter
149    # By default, the probe filter size is configured to be twice the
150    # size of the L2 cache.
151    #
152    pf_size = MemorySize(options.l2_size)
153    pf_size.value = pf_size.value * 2
154    dir_bits = int(math.log(options.num_dirs, 2))
155    pf_bits = int(math.log(pf_size.value, 2))
156    if options.numa_high_bit:
157        if options.pf_on or options.dir_on:
158            # if numa high bit explicitly set, make sure it does not overlap
159            # with the probe filter index
160            assert(options.numa_high_bit - dir_bits > pf_bits)
161
162        # set the probe filter start bit to just above the block offset
163        pf_start_bit = block_size_bits
164    else:
165        if dir_bits > 0:
166            pf_start_bit = dir_bits + block_size_bits - 1
167        else:
168            pf_start_bit = block_size_bits
169
170    # Run each of the ruby memory controllers at a ratio of the frequency of
171    # the ruby system
172    # clk_divider value is a fix to pass regression.
173    ruby_system.memctrl_clk_domain = DerivedClockDomain(
174                                          clk_domain=ruby_system.clk_domain,
175                                          clk_divider=3)
176
177    mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
178        options, bootmem, ruby_system, system)
179    dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
180    if rom_dir_cntrl_node is not None:
181        dir_cntrl_nodes.append(rom_dir_cntrl_node)
182    for dir_cntrl in dir_cntrl_nodes:
183        pf = ProbeFilter(size = pf_size, assoc = 4,
184                         start_index_bit = pf_start_bit)
185
186        dir_cntrl.probeFilter = pf
187        dir_cntrl.probe_filter_enabled = options.pf_on
188        dir_cntrl.full_bit_dir_enabled = options.dir_on
189
190        if options.recycle_latency:
191            dir_cntrl.recycle_latency = options.recycle_latency
192
193        # Connect the directory controller to the network
194        dir_cntrl.forwardFromDir = MessageBuffer()
195        dir_cntrl.forwardFromDir.master = ruby_system.network.slave
196        dir_cntrl.responseFromDir = MessageBuffer()
197        dir_cntrl.responseFromDir.master = ruby_system.network.slave
198        dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
199        dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
200
201        dir_cntrl.triggerQueue = MessageBuffer(ordered = True)
202
203        dir_cntrl.unblockToDir = MessageBuffer()
204        dir_cntrl.unblockToDir.slave = ruby_system.network.master
205        dir_cntrl.responseToDir = MessageBuffer()
206        dir_cntrl.responseToDir.slave = ruby_system.network.master
207        dir_cntrl.requestToDir = MessageBuffer()
208        dir_cntrl.requestToDir.slave = ruby_system.network.master
209        dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
210        dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
211        dir_cntrl.responseFromMemory = MessageBuffer()
212
213
214    for i, dma_port in enumerate(dma_ports):
215        #
216        # Create the Ruby objects associated with the dma controller
217        #
218        dma_seq = DMASequencer(version = i,
219                               ruby_system = ruby_system,
220                               slave = dma_port)
221
222        dma_cntrl = DMA_Controller(version = i,
223                                   dma_sequencer = dma_seq,
224                                   transitions_per_cycle = options.ports,
225                                   ruby_system = ruby_system)
226
227        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
228        dma_cntrl_nodes.append(dma_cntrl)
229
230        if options.recycle_latency:
231            dma_cntrl.recycle_latency = options.recycle_latency
232
233        # Connect the dma controller to the network
234        dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
235        dma_cntrl.responseFromDir.slave = ruby_system.network.master
236        dma_cntrl.requestToDir = MessageBuffer()
237        dma_cntrl.requestToDir.master = ruby_system.network.slave
238        dma_cntrl.mandatoryQueue = MessageBuffer()
239
240    all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
241
242    # Create the io controller and the sequencer
243    if full_system:
244        io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
245        ruby_system._io_port = io_seq
246        io_controller = DMA_Controller(version = len(dma_ports),
247                                       dma_sequencer = io_seq,
248                                       ruby_system = ruby_system)
249        ruby_system.io_controller = io_controller
250
251        # Connect the dma controller to the network
252        io_controller.responseFromDir = MessageBuffer(ordered = True)
253        io_controller.responseFromDir.slave = ruby_system.network.master
254        io_controller.requestToDir = MessageBuffer()
255        io_controller.requestToDir.master = ruby_system.network.slave
256        io_controller.mandatoryQueue = MessageBuffer()
257
258        all_cntrls = all_cntrls + [io_controller]
259    # Register configuration with filesystem
260    else:
261        for i in xrange(options.num_cpus):
262            FileSystemConfig.register_cpu(physical_package_id = 0,
263                                          core_siblings = [],
264                                          core_id = i,
265                                          thread_siblings = [])
266
267            FileSystemConfig.register_cache(level = 1,
268                                            idu_type = 'Instruction',
269                                            size = options.l1i_size,
270                                            line_size = options.cacheline_size,
271                                            assoc = options.l1i_assoc,
272                                            cpus = [i])
273            FileSystemConfig.register_cache(level = 1,
274                                            idu_type = 'Data',
275                                            size = options.l1d_size,
276                                            line_size = options.cacheline_size,
277                                            assoc = options.l1d_assoc,
278                                            cpus = [i])
279
280            FileSystemConfig.register_cache(level = 2,
281                                            idu_type = 'Unified',
282                                            size = options.l2_size,
283                                            line_size = options.cacheline_size,
284                                            assoc = options.l2_assoc,
285                                            cpus = [i])
286
287    ruby_system.network.number_of_virtual_networks = 6
288    topology = create_topology(all_cntrls, options)
289    return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
290