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14284:41f38d022533 |
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12-Aug-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Conditionally enable HDLcd when doing DTB autogen
This is a preparation change for a real DTB autogen implementation
Change-Id: Ia0c1c5e65ea96036e55455eb4222cec12944d33a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20331 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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#
14283:b02cde4661e1 |
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12-Aug-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Add HDLcd DTB autogeneration
A Display has been defined. Its sole purpose is to generate the device tree node to be referenced by the HDLcd device. The encoder parameters are based on the existing node defined in:
system/arm/dt/armv8.dts
Change-Id: I6cdeb0437dce207dbd0f2c65c16b224245eb74e1 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20330 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14274:8fc8b95931aa |
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14-Aug-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Allow IOMMU binding to HDLcd
Change-Id: I894080e7bd76e7efedef141c937e1561c0c0527c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20841 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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14225:8df8b95062ed |
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22-Aug-2019 |
Adrian Herrera <adrian.herrera@arm.com> |
dev-arm: modify GICv3 ITS default addr
The current default base address for GICv3 ITS stated in RealView is 0x2c120000. The redistributors base address is 0x2c010000; each instantiated core has an associated redistributor with memory region size 0x40000 (with GICv4 extension, enabled by default). With 8 cores, the redistributor range spans to 0x2c210000, creating a conflict with the ITS address space.
This patch changes the ITS base address to 0x2e010000 which guarantees no overlapping with the redistributor.
Change-Id: I7dc1af9e69ac037f85ae96f0985554f1fb8372a0 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20608 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14153:03d1ad4167b0 |
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09-Aug-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Fix PCI node's interrupt-map property
The PCI host has an interrupt-map property which only works for a fixed setup of parent/child interrupt/address cells, which currently overlaps with GICv2. We want to make this flexible, so that the interrupt-map doesn't break if we change the interrupt/address-cells value, and the patch is aiming in that direction. This is also needed for GICv3 DTB autogeneration, since it is using different values than GICv2.
Change-Id: If1c661ddcbc0c277c9d6b0e44a0fd3fe2427618c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20052 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13996:8a567118e670 |
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16-Apr-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Provide a GICv3 ITS Implementation
This patch introduces the GICv3 ITS module, which is in charge of translating MSIs into physical (GICv3) and virtual (GICv4) LPIs. The patch is only GICv3 compliant, which means that there is no direct virtual LPI injection (this also means V* commands are unimplemented) Other missing features are:
* No 2level ITS tables (only flat table supported)
* Command errors: when there is an error in the ITS, it is IMPLEMENTATION DEFINED on how the ITS behaves. There are three possible scenarios (see GICv3 TRM) and this implementation only supports one of these (which is, aborting the command and jumping to the next one). Furter patches could make it possible to select different reactions
* Invalidation commands (INV, INVALL) are only doing the memory table walks, assuming the current Gicv3Redistributor is not caching any configuration table entry.
Change-Id: If4ae9267ac1de7b20a04986a2af3ca3109743211 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18601 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13880:856d3436a90d |
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16-Apr-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Move GICv3 (Re)Ditributor address in Realview.py
Base addresses for GICv3's Distributor and Redistributors are implementation defined: they depend on the platform rather than the model. This patch is then moving dist_addr and redist_addr initialization in Realview.py
Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13879:15323aaa832f |
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05-Apr-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Limit number of max PE in GICv3 to 128
This is needed since there is a problem in the memory layout of VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping regions when reserving space for 256 PEs.
GICv3 redistributors: 0x2c010000 - 0x30010000 PCI regions: 0x30000000 - 0x40000000
We fix this by cutting down the number of supported PEs to 128
Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13826:34a9929c35eb |
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18-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13814:90cdf66cca54 |
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18-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Rename GIC maintenance interrupt from ppint to maint_int
ppint is a generic name which only reflects Arm recommendation of assigning the maintanance interrupt to a PPI (numbered 25)
Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13805:f6d331fa1303 |
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25-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Set/Unset dma coherent mode from python
With this patch it will be possible to automatically enable/disable the dma-coherent property for the GenericArmPciHost autogenerated DTB. This has been done by adding the _dma_coherent param.
Change-Id: I1759fced74e42410462637ca77997a351314a90a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13665:9c7fe3811b88 |
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25-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Don't assume SimObjects live in the global namespace
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files.
Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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13636:3b55e4bae1d8 |
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04-Feb-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
configs, arch-arm: Using AddrRange for Realview mem_regions
Physical memory ranges are now saved in Realview objects as pairs of addresses (start address and size). This patch is substituting them with a single AddrRange object.
Change-Id: I02d25d557c5c54d062f0dccef8ede45744d0ce6b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16206 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13532:b1cacf73cd4e |
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13-Nov-2018 |
Jairo Balart <jairo.balart@metempsy.com> |
dev-arm: Add a VExpress_GEM5_V2 platform with GICv3 support
Change-Id: I6fd14138d94654e8e60cde08239ea9a50fc19eb7 Reviewed-on: https://gem5-review.googlesource.com/c/14255 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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13505:e699fce12780 |
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21-Dec-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Implement GIC-400 model from GicV2
Implementation registers for the GICv2 model currently hold values referring to a GIC-400 implementation. This patch is making them parametrizable so that it is possible to instantiate a GIC-400 model. The patch is also modifying Realview platform to use new GIC-400 model in lieau of GICv2.
Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15277 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13504:5a01198080fa |
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20-Dec-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Move VGic from Realview.py to Gic.py
Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15276 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13167:258a04d4c20b |
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04-Sep-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
dev, arm: remove the RealViewEB platform
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it.
Furthermore, trying to use it fails with:
object 'RealViewEB' has no attribute 'pci_host'
and the last commit in the class happened two years ago, which indicates that no one has been using it.
Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13106:3af014b59080 |
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11-Sep-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Make CpuLocalTimer use standard ArmInterruptPin
Change-Id: I8c4eb9389b47df8cdf1eec966bb2c9da85a7a7c8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12744 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13016:b15b89f28870 |
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12-Sep-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
dev-arm: fix build to missing Pl390 to Gicv2 rename
Change-Id: I6756f2c789aaca410d201aa64147443b66afee39 Reviewed-on: https://gem5-review.googlesource.com/12645 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13015:9e48c6a83b85 |
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30-Aug-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
config, dev-arm: Fix UART handling baremetal mode
fs.py in baremetal mode currently fails for the VExpress_GEM5_V1 platform due to inconsistent UART naming with error message:
AttributeError: object 'VExpress_GEM5_V1' has no attribute 'uart'
Consistently name keep all UARTs in the Arm platforms in a vector named 'uart' or as a single device named 'uart'. Update the configuration scripts to reflect the fact that 'uart' can be a vector.
Change-Id: I20b8dbac794d6a9be19b6ce8c335a097872132fb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12473 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13014:a4f71c3dc602 |
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30-Aug-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
dev-arm: rename Pl390 to GicV2
The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features.
GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one.
Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13013:b204ddd2b986 |
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30-Aug-2018 |
Ciro Santilli <ciro.santilli@arm.com> |
dev-arm: improve Pl390 parameters
Remove default dist_addr and cpu_addr register addresses since those are purely platform specific.
Parametrize the cpu_size parameter. RealViewPBX has the Gic CPU and distributor base too close for the newer CPU size of 0x2000, leading to overlap.
This was introduced in I90a9f669a46a37d79c6cc542087cf91f2044f104 and makes using RealViewPBX fail with:
fatal: system.membus has two ports responding within range [0x1f000100 : 0x1f0020ff]: system.realview.gic.pio system.realview.gic.pio
Change-Id: Ic6c0e6b3d4705ff369eb739d54a1173a47819b7d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12491 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12975:f521b0fcc17c |
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30-Aug-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev-arm: Make GenericTimer use standard ArmInterruptPin
This patch is deleting the custom ArchTimer::Interrupt implementation in favour of the standard ArmInterruptPin.
Change-Id: I5aa5661e48834398bd7aae15df9578b8db5c8da3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12402 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12896:bac7d22c1660 |
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18-Jul-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Fix incorrect GIC address range sizes
The GICv2 specifies that 8KiB of the memory map is allocated to the CPU interface and 4KiB is allocated to the distributor. The current distributor size is off by 1 and the CPU interface is completely off by a lot.
Change-Id: I90a9f669a46a37d79c6cc542087cf91f2044f104 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11769
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12785:9afd7453ccdb |
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05-Jun-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev-arm: Use recurseDeviceTree instead of custom in platform
The platform code uses a custom mechanism to traverse the object hierarchy when generating device trees. This is highly undesirable since this breaks for common cases such as when SimObjects are stored in a list.
Change-Id: I1b968e5fa1db62f1456e3c0ac3de47ab1299e58d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10781 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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12760:145d5c512cfc |
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23-Mar-2018 |
Rohit Kurup <rohit.kurup@arm.com> |
dev-arm: Add new VExpress_GEM5_V1_Base Platform
Add a new VExpress_GEM5_V1_Base Platform which configures basic on chip devices. The original VExpress_GEM5_V1 will inherit the Base and add more on chip devices (currently only the HDLCD). This change will make it possible to create variations of the base platform with different devices.
Change-Id: I21f9bf4f6217d87e811ff777f630122593eef013 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10807 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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12741:6d088ffe06b1 |
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24-Mar-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev-arm: Add a VirtIO MMIO device to VExpress_GEM5_V1
Add an ARM-specific VirtIO MMIO device to the VExpress_GEM5_V1 platform.
Change-Id: Id1e75398e039aad9d637f46f653cda9084d3d2fe Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2327
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12733:fd6b0c5419aa |
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22-Feb-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Add support for HYP & secure timers
Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10023 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
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12664:4e4555947641 |
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09-Apr-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Cleanup Pl050 interrupt handling
Add support for TX interrupts and cleanup existing RX interrupt handling.
Change-Id: If2e5b0c0cc6fbeb2dce09e7e9d935647516b2c47 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9769
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12659:3b44e9f66aac |
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09-Apr-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Use the PS/2 framework in the Pl050 model
The Pl050 KMI model currently has its own keyboard and mouse models. Use the generic PS/2 interface instead.
Change-Id: I6523d26f8e38bcc8ba399d4d1a131723645d36c7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9767 Reviewed-by: Gabe Black <gabeblack@google.com>
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12598:b80b2d9a251b |
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12-Feb-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
arch-arm, configs: Treat the bootloader rom as cacheable memory
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller.
Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12474:31aaa43d1401 |
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22-Jan-2016 |
Glenn Bergmans <glenn.bergmans@arm.com> |
arm: DT autogeneration - generate PCI node
Enables automatic generation of Device Trees for RealView PCI host controllers. Note that some parts are more hard coded than you'd want, but this is due to the limited understanding the PCI host has of its configuration (i.e. it doesn't know all memory ranges). Fixing this, for now at least, went beyond the scope and intentions of the Device Tree generating code: use with care!
Change-Id: I2041871e0eb4d04fb5191257c47dd38649d1c0cc Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5967 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12472:3cbae56f402d |
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17-Dec-2015 |
Glenn Bergmans <glenn.bergmans@arm.com> |
arm: DT autogeneration - autogenerate RealView Platform devices
Implements the Device Tree generating code for devices required by the RealView VExpress_GEM5_V1 platform
Change-Id: I14244b2f3c028cbddba3c23ce7433fe3b301a0e8 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5965 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12467:087fab1b0e54 |
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07-Sep-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
arm: make Arm GenericTimer a ClockedObject
Within a device tree, the GenericTimer device needs to point (via phandle) to a clock domain which is itself also an object in the device tree. Within gem5, clock domains are managed by making all clocked SimObjects inherit from ClockedObject rather than SimObject.
Without this change, the GenericTimer is unable to generate the appropriate clock domain phandle, and will crash during DTB autogeneration.
Change-Id: I6d3fb6362847c6a01720b2f14b3d595d1e59f01f Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4960 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12272:bcc67ee98e6d |
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12-May-2016 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
sim: Implement load_addr_mask auto-calculation
Recent Linux kernels for AArch64 have changed their start addresses but we still want to relocate the kernel to 0x80080000 which required hacking the load_addr_mask in Realview.py to be 0x7ffffff from 0xfffffff to mask off the proper number of MSBs to load the kernel in the desired location. To avoid having to make this change in the future again, we auto-calculate the load_addr_mask if it is specified as 0x0 in the System sim-object to find the most restrictive address mask instead of having the configuration specify it. If the configuration does specify the address mask, we use it instead of auto-calculating.
Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2323 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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#
12232:20817121988b |
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28-Sep-2017 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
dev: Using Configurable image writer in HDLcd
The fixed image writer (which was dumping .bmp images only) has been replaced by the configurable one in HDLcd device. Default format is Auto, which gives gem5 the freedom to choose the format it prefers.
Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12116:5aeb6cc0993a |
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28-Jun-2017 |
Jose Marinho <jose.marinho@arm.com> |
dev-arm: Don't unconditionally overwrite bootloader params
The bootloader arguments were previously defaulting to a predetermined value even if initialized elsewhere in the platform config script. This commit fixes this issue by not calling the default initialization routine if the bootloader is already defined.
Change-Id: Id80af4762b52dc036da29430b2795bb30970a349 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3967
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#
12077:3c014d139dc7 |
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23-Feb-2017 |
Gedare Bloom <gedare@rtems.org> |
dev, arm: add a9mpcore global timer device
Change-Id: I6d8a5e3795291b2a4cce022f555cf4b04f997538 Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3262 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12069:6554872926ec |
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29-Mar-2017 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
arm: Refactor the VExpress_EMM system creation
Change-Id: Iac3d15719b2bbc426020a27d6b47a4baaab078c7 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2907 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12059:bf8ec28e7a76 |
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12-Jan-2017 |
Weiping Liao <weipingliao@google.com> |
config: Adjust load_addr_mask in VExpress_GEM5_V1
Fix load_addr_mask in VExpress_GEM5_V1 in order to boot with the 64-bit kernel.
Change-Id: I13a0a752c60e53262a245cb24b16606071041397 Reviewed-on: https://gem5-review.googlesource.com/3643 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12006:aebe66ac7a3d |
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28-Apr-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Enable m5ops by default for VExpress_GEM5_V1
Allocate 0x10010000-0x1001ffff for m5 pseudo-ops. This range is a part of the CS5 address range in the RS1/RS2 memory map.
Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2965
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11898:cada5b68fb12 |
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01-Mar-2017 |
Sudhanshu Jha <sudhanshu.jha@arm.com> |
dev, arm: Render HDLCD frames at a fixed rate in KVM
Use the new fast scan-out API in the PixelPump to render frames at a fixed frame rate in KVM mode. The refresh rate when running in KVM can be controlled by the virt_refresh_rate parameter.
Change-Id: Ib3c78f174e3f8f4ca8a9b723c4e5d311a433b8aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2242 Reviewed-by: Rahul Thakur <rjthakur@google.com>
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11841:16dec978b549 |
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14-Feb-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm, kvm: Automatically use the MuxingKvmGic
Automatically use the MuxingKvmGic in the VExpress_GEM5_V1 platform. This removes the need to patch the host kernel or the platform configuration when using KVM on ARM.
Change-Id: Ib1ed9b3b849b80c449ef1b62b83748f3f54ada26 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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11668:380375085863 |
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07-Oct-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Make GenericTimer param handling more robust
The generic timer needs a pointer to an ArmSystem to wire itself to the system register handler. This was previously specified as an instance of System that was later cast to ArmSystem. Make this more robust by specifying it as an ArmSystem in the Python interface and add a check to make sure that it is non-NULL.
Change-Id: I989455e666f4ea324df28124edbbadfd094b0d02 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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11597:da2c13f1b2e1 |
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10-Aug-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm, dev: Add support for listing DMA ports in new platforms
When using a Ruby memory system, the Ruby configuration scripts expect to get a list of DMA ports to create the necessary DMA sequencers. Add support in the utility functions that wire up devices to append DMA ports to a list instead of connecting them to the IO bus. These functions are currently only used by the VExpress_GEM5_V1 platform.
Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
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11595:5c6e658fd90c |
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10-Aug-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Don't report the boot ROM as a memory in config tables
The boot ROM shouldn't be used as a memory by the kernel. Memories have a flag to indicate this which is set for some platforms. Update all platforms to consistently set this flag to indicate that the boot ROM shouldn't be reported as normal memory.
Change-Id: I2bf0273e99d2a668e4e8d59f535c1910c745aa7b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
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11421:74c1e6513bd0 |
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13-May-2015 |
David Guillen Fandos <david.guillen@arm.com> |
sim: Thermal support for Linux
This patch enables Linux to read the temperature using hwmon infrastructure. In order to use this in your gem5 you need to compile the kernel using the following configs:
CONFIG_HWMON=y CONFIG_SENSORS_VEXPRESS=y
And a proper dts file (containing an entry such as):
dcc { compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>;
temp@0 { compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "DCC"; }; };
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11297:d1f8610cdffd |
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15-Jan-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Add a platform with support for both aarch32 and aarch64
Add a platform with support for both aarch32 and aarch64. This platform implements a subset of the devices in a real Versatile Express and extends it with some gem5-specific functionality. It is in many ways similar to the old VExpress_EMM64 platform, but supports the following new features:
* Automatic PCI interrupt assignment * PCI interrupts allocated in a contiguous range. * Automatic boot loader selection (32-bit / 64-bit) * Cleaner memory map where gem5-specific devices live in CS5 which isn't used by current Versatile Express platforms. * No fake devices. Devices that were previously faked will be removed from the device tree instead. * Support for 510 GiB contiguous memory
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11296:fe89fe1d1869 |
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15-Jan-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Add support for automatic PCI interrupt routing
Add support for automatic PCI interrupt routing using a device's ID on the PCI bus. Our current DTBs typically tell the kernel that we do this or something similar when declaring the PCI controller. This changeset adds an option to make the simulator behave in the same way.
Interrupt routing can be selected by setting the int_policy parameter in the GenericArmPciHost. The following values are supported:
* ARM_PCI_INT_STATIC: Use the old static routing policy using the interrupt line from a device's configurtion space.
* ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an interrupt in the GIC. The interrupt is computed as:
gic_int = int_base + (pci_dev % int_count)
* ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to an interrupt in the GIC. The PCI specification reserves pin ID 0 for devices without interrupts, the interrupt therefore computed as:
gic_int = int_base + ((pin - 1) % int_count)
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11244:a2af58a06c4e |
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04-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev: Rewrite PCI host functionality
The gem5's current PCI host functionality is very ad hoc. The current implementations require PCI devices to be hooked up to the configuration space via a separate configuration port. Devices query the platform to get their config-space address range. Un-mapped parts of the config space are intercepted using the XBar's default port mechanism and a magic catch-all device (PciConfigAll).
This changeset redesigns the PCI host functionality to improve code reuse and make config-space and interrupt mapping more transparent. Existing platform code has been updated to use the new PCI host and configured to stay backwards compatible (i.e., no guest-side visible changes). The current implementation does not expose any new functionality, but it can easily be extended with features such as automatic interrupt mapping.
PCI devices now register themselves with a PCI host controller. The host controller interface is defined in the abstract base class PciHost. Registration is done by PciHost::registerDevice() which takes the device, its bus position (bus/dev/func tuple), and its interrupt pin (INTA-INTC) as a parameter. The registration interface returns a PciHost::DeviceInterface that the PCI device can use to query memory mappings and signal interrupts.
The host device manages the entire PCI configuration space. Accesses to devices decoded into the devices bus position and then forwarded to the correct device.
Basic PCI host functionality is implemented in the GenericPciHost base class. Most platforms can use this class as a basic PCI controller. It provides the following functionality:
* Configurable configuration space decoding. The number of bits dedicated to a device is a prameter, making it possible to support both CAM, ECAM, and legacy mappings.
* Basic interrupt mapping using the interruptLine value from a device's configuration space. This behavior is the same as in the old implementation. More advanced controllers can override the interrupt mapping method to dynamically assign host interrupts to PCI devices.
* Simple (base + addr) remapping from the PCI bus's address space to physical addresses for PIO, memory, and DMA.
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11237:2d5d847aab27 |
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03-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Disable R/B swap in HDLCD by default
The HDLCD model implements a workaround that swaps the red and blue channels. This works around an issue in certain old kernels. The new driver doesn't seem to have this behavior, so disable the workaround by default and enable it in the affected platforms.
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11236:3232a75ed9c0 |
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03-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Split MCC and DCC subsystems
Devices behind the Versatile Express configuration controllers are currently all lumped into one SimObject. This will make DTB generation challenging since the DTB assumes them to be in different parts of the hierarchy. It also makes it hard to model other CoreTiles without also replicating devices from the motherboard.
This changeset splits the VExpressCoreTileCtrl into two subsystems: VExpressMCC for all motherboard-related devices and CoreTile2A15DCC for Core Tile specific devices.
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11090:f37a6b82f98f |
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11-Sep-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Rewrite the HDLCD controller
Rewrite the HDLCD controller to use the new DMA engine and pixel pump. This fixes several bugs in the current implementation:
* Broken/missing interrupt support (VSync, underrun, DMA end) * Fragile resolution changes (changing resolutions used to cause assertion errors). * Support for resolutions with a width that isn't divisible by 32. * The pixel clock can now be set dynamically.
This breaks checkpoint compatibility. Checkpoints can be upgraded with the checkpoint conversion script. However, upgraded checkpoints won't contain the state of the current frame. That means that HDLCD controllers restoring from a converted checkpoint immediately start drawing a new frame (i.e, expect timing differences).
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11011:2ca6c68fdd6c |
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07-Aug-2015 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm: Add support for programmable oscillators
Add support for oscillators that can be programmed using the RealView / Versatile Express configuration interface. These oscillators are typically used for things like the pixel clock in the display controller.
The default configurations support the oscillators from a Versatile Express motherboard (V2M-P1) with a CoreTile Express A15x2.
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10847:1826ee736709 |
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23-May-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm, dev: Add support for a memory mapped generic timer
There are cases when we don't want to use a system register mapped generic timer, but can't use the SP804. For example, when using KVM on aarch64, we want to intercept accesses to the generic timer, but can't do so if it is using the system register interface. In such cases, we need to use a memory-mapped generic timer.
This changeset adds a device model that implements the memory mapped generic timer interface. The current implementation only supports a single frame (i.e., one virtual timer and one physical timer).
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10845:75df7a87be83 |
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23-May-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Add virtual timers to the generic timer model
The generic timer model currently does not support virtual counters. Virtual and physical counters both tick with the same frequency. However, virtual timers allow a hypervisor to set an offset that is subtracted from the counter when it is read. This enables the hypervisor to present a time base that ticks with virtual time in the VM (i.e., doesn't tick when the VM isn't running). Modern Linux kernels generally assume that virtual counters exist and try to use them by default.
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10844:8551af601f75 |
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23-May-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
dev, arm: Refactor and clean up the generic timer model
This changeset cleans up the generic timer a bit and moves most of the register juggling from the ISA code into a separate class in the same source file as the rest of the generic timer. It also removes the assumption that there is always 8 or fewer CPUs in the system. Instead of having a fixed limit, we now instantiate per-core timers as they are requested. This is all in preparation for other patches that add support for virtual timers and a memory mapped interface.
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10840:48039363f67a |
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23-May-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm: Workaround incorrect HDLCD register order in kernel
Some versions of the kernel incorrectly swap the red and blue color select registers. This changeset adds a workaround for that by swapping them when instantiating a PixelConverter.
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10780:46070443051e |
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08-Apr-2015 |
Curtis Dunham <Curtis.Dunham@arm.com> |
config: Support full-system with SST's memory system
This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories.
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10397:3064e1beeb49 |
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25-Jul-2014 |
Stephan Diestelhorst <stephan.diestelhorst@arm.com> |
energy: Add the Energy Controller in the right configs
Tie in the newly created energy controller components in the default configurations.
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10358:644b615fbe6a |
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03-Sep-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm: Support >2GB of memory for AArch64 systems
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10356:198dfef33403 |
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03-Sep-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
dev, arm: Add support for linux generic pci host driver
This change adds support for a generic pci host bus driver that has been included in recent Linux kernel instead of the more bespoke one we've been using to date. It also works with aarch64 so it provides PCI support for 64-bit ARM Linux.
To make this work a new configuration option pci_io_base is added to the RealView platform that should be set to the start of the memory used as memory mapped IO ports (IO ports that are memory mapped, not regular memory mapped IO). And a parameter pci_cfg_gen_offsets which specifies if the config space offsets should be used that the generic driver expects.
To use the pci-host-generic device you need to: pci_io_base = 0x2f000000 (Valid for VExpress EMM) pci_cfg_gen_offsets = True
and add the following to your device tree:
pci { compatible = "pci-host-ecam-generic"; device_type = "pci"; #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; //bus-range = <0x0 0x1>;
// CPU_PHYSICAL(2) SIZE(2) // Note, some DTS blobs only support 1 size reg = <0x0 0x30000000 0x0 0x10000000>;
// IO (1), no bus address (2), cpu address (2), size (2) // MMIO (1), at address (2), cpu address (2), size (2) ranges = <0x01000000 0x0 0x00000000 0x0 0x2f000000 0x0 0x10000>, <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x10000000>;
// With gem5 we typically use INTA/B/C/D one per device interrupt-map = <0x0000 0x0 0x0 0x1 0x1 0x0 0x11 0x1 0x0000 0x0 0x0 0x2 0x1 0x0 0x12 0x1 0x0000 0x0 0x0 0x3 0x1 0x0 0x13 0x1 0x0000 0x0 0x0 0x4 0x1 0x0 0x14 0x1>;
// Only match INTA/B/C/D and not BDF interrupt-map-mask = <0x0000 0x0 0x0 0x7>; };
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10353:dfebd39c48a7 |
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03-Sep-2014 |
Geoffrey Blake <Geoffrey.Blake@arm.com> |
config: Refactor RealviewEMM to fit into new config system
This eliminates some default devices and adds in helper functions to connect the devices defined here to associate with the proper clock domains.
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10187:7fef26827810 |
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09-May-2014 |
Chris Emmons <Chris.Emmons@arm.com> |
dev: Set HDLCD default pixel clock for 1080p @ 60Hz
This patch changes the default pixel clock to effectively generate 1080p resolution at 60 frames per second. It is dependent upon the kernel device tree file using the specified resolution / display string in the comments.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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9939:735d73e394d3 |
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17-Oct-2013 |
Dam Sunwoo <dam.sunwoo@arm.com> |
dev: Add option to disable framebuffer .bmp dump in run folder
There is an option to enable/disable all framebuffer dumps, but the last frame always gets dumped in the run folder with no other way to disable it. These files can add up very quickly running many experiments.
This patch adds an option to disable them. The default behavior remains unchanged.
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9835:cc7a7fc71c42 |
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19-Aug-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
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9806:3f262c18ad5d |
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11-Jul-2013 |
Steve Reinhardt <stever@gmail.com> |
dev/arm: get rid of AmbaDev namespace
It was confusing having an AmbaDev namespace along with an AmbaDevice class. The namespace stuff is now moved in to a new base AmbaDevice class, which is a mixin for classes AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice to provide the readId function as an inherited member function.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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9788:5558ee8dd7d9 |
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27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour.
The main motivation for these simplifications is to ease the introduction of clock domains.
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9707:1305bec2733f |
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30-May-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Avoid explicitly zeroing the memory backing store
This patch removes the explicit memset as it is redundant and causes the simulator to touch the entire space, forcing the host system to allocate the pages.
Anonymous pages are mapped on the first access, and the page-fault handler is responsible for zeroing them. Thus, the pages are still zeroed, but we avoid touching the entire allocated space which enables us to use much larger memory sizes as long as not all the memory is actually used.
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9646:7a0c51f14095 |
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22-Apr-2013 |
Chris Emmons <Chris.Emmons@arm.com> |
ARM: Add support for HDLCD controller for TC2 and newer Versatile Express tiles.
Newer core tiles / daughterboards for the Versatile Express platform have an HDLCD controller that supports HD-quality output. This patch adds an implementation of the controller.
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9525:0587c8983d47 |
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25-Oct-2012 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
arm: Create a GIC base class and make the PL390 derive from it
This patch moves the GIC interface to a separate base class and makes all interrupt devices use that base class instead of a pointer to the PL390 implementation. This allows us to have multiple GIC implementations. Future implementations will allow in-kernel GIC implementations when using hardware virtualization.
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9394:e88cf95d33d3 |
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07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
dev: Fix the Pl111 timings by separating pixel and DMA clock
This patch fixes the Pl111 timings by creating a separate clock for the pixel timings. The device clock is used for all interactions with the memory system, just like the AHB clock on the actual module.
The result without this patch is that the module only is allowed to send one request every tick of the 24MHz clock which causes a huge backlog.
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9387:175421e57fff |
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07-Jan-2013 |
Chris Emmons <Chris.Emmons@arm.com> |
config: Replace second keyboard with a mouse.
The platform has two KMI devices that are both setup to be keyboards. This patch changes the second keyboard to a mouse. This patch will allow keyboard input as usual and additionally provide mouse support.
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9338:97b4a2be1e5b |
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02-Nov-2012 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy.
This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
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9330:4a3269a11230 |
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02-Nov-2012 |
Chander Sudanthi <chander.sudanthi@arm.com> |
base: split out the VncServer into a VncInput and Server classes
This patch adds a VncInput base class which VncServer inherits from. Another class can implement the same interface and be used instead of the VncServer, for example a class that replays Vnc traffic.
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9185:1d0f46a90f91 |
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07-Sep-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix one of the timers used in the VExpress EMM platform.
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#
9157:e0bad9d7bbd6 |
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21-Aug-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Clock: Move the clock and related functions to ClockedObject
This patch moves the clock of the CPU, bus, and numerous devices to the new class ClockedObject, that sits in between the SimObject and MemObject in the class hierarchy. Although there are currently a fair amount of MemObjects that do not make use of the clock, they potentially should do so, e.g. the caches should at some point have the same clock as the CPU, potentially with a 1:n ratio. This patch does not introduce any new clock objects or object hierarchies (clusters, clock domains etc), but is still a step in the direction of having a more structured approach clock domains.
The most contentious part of this patch is the serialisation of clocks that some of the modules (but not all) did previously. This serialisation should not be needed as the clock is set through the parameters even when restoring from the checkpoint. In other words, the state is "stored" in the Python code that creates the modules.
The nextCycle methods are also simplified and the clock phase parameter of the CPU is removed (this could be part of a clock object once they are introduced).
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#
9073:f75ee4849c40 |
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27-Jun-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix address range issue with VExpress EMM
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#
9052:acd6ffe55960 |
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05-Jun-2012 |
Geoffrey Blake <geoffrey.blake@arm.com> |
ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT
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9000:6c2381ecdfbc |
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10-May-2012 |
Chander Sudanthi <Chander.Sudanthi@arm.com |
ARM: EMM board address range fix
0x40000000 is reservered for external AXI addresses. This address range is not used currently. Removed the range from the bridge.
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#
8931:7a1dfb191e3f |
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06-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range.
All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables.
Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation.
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#
8906:b04b87b6ad84 |
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21-Mar-2012 |
Koan-Sin Tan <koansin.tan@gmail.com> |
ARM: Add RTC to PBX System
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8872:9f1c4729d89d |
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01-Mar-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: FIx missing cf controller connection.
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8870:f95c4042f2d0 |
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01-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
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#
8847:ef8630054b5e |
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14-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Fix residual bus ports and make them master/slave
This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level.
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8839:eeb293859255 |
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13-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port.
Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
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#
8810:00f0d0230596 |
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01-Feb-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
configs: More fixes for the memory system updates
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#
8799:dac1e33e07b0 |
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28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with the main repo.
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8742:9df38d259935 |
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04-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Put platform pointers in fewer objects.
Not all objects need a platform pointer, and having one creates a dependence on their being a platform object. This change removes the platform pointer to from the base device object and moves it into subclasses that actually need it.
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#
8714:cd48e2802644 |
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17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Removing the default port peer from Python ports
In preparation for the introduction of Master and Slave ports, this patch removes the default port parameter in the Python port and thus forces the argument list of the Port to contain only the description. The drawback at this point is that the config port and dma port of PCI and DMA devices have to be connected explicitly. This is key for future diversification as the pio and config port are slaves, but the dma port is a master.
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#
8713:2f1a3e335255 |
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17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities.
In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.
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#
8525:5f3fe76e7950 |
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19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add VExpress_E support with PCIe to gem5
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#
8524:1ddd1aa0e55b |
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19-Aug-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for Versatile Express boards
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8512:a508c2d92d63 |
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19-Aug-2011 |
Geoffrey Blake <geoffrey.blake@arm.com> |
ARM: Add per-cpu local timers for ARM.
Cortex-A9 processors can have a local timer and watchdog counter. It is enabled by default in Linux and up to this point we've had to disable them since a model wasn't available. This change allows a default MP ARM Linux configuration to boot.
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#
8461:7d0669201f80 |
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10-Jul-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
IO: Handle case where ISA Fake device is being used as a fake memory.
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#
8299:64a938a8b7fc |
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13-May-2011 |
Chander Sudanthi <chander.sudanthi@arm.com> |
ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board. Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl respectively.
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#
8283:ea5a46abdcca |
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04-May-2011 |
Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> |
ARM: Make GIC handle IPIs and multiple processors.
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#
8282:0cc4594abf28 |
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04-May-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add snoop control unit device.
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8212:134bd699967a |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Include IDE/CF controller by default in PBX model.
Frame buffer and boot linux: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxFrameBuf --kernel=vmlinux.touchkit Linux from a CF card: ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.touchkit Run Android ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmAndroid --kernel=vmlinux.android Run MP ./build/ARM_FS/m5.opt configs/example/fs.py --benchmark=ArmLinuxCflash --kernel=vmlinux.mp-2.6.38
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#
7950:1120b07dd4b0 |
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11-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
VNC/ARM: Use VNC server and add support to boot into X11
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#
7754:8ae6f4055594 |
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15-Nov-2010 |
William Wang <William.Wang@arm.com> |
ARM: Add a Keyboard Mouse Interface controller
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#
7753:d3e613312953 |
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15-Nov-2010 |
William Wang <William.Wang@arm.com> |
ARM: Implement a CLCD Frame buffer
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#
7731:e1eace3a118a |
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08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Keep the warnings to a minimum.
These warnings still need to be addresses, but pages of them is counterproductive.
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#
7696:1e789578729e |
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01-Oct-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add a fake flash controller so that unmodified linux can boot
With this change an unmodified Linux kernel can boot in M5.
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#
7587:177151a54462 |
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23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
ARM: Change how the AMBA device ID checking is done to make it more generic
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#
7584:28ddf6d9e982 |
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23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
ARM: Add I/O devices for booting linux
|