RealView.py revision 9939:735d73e394d3
1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54 55class AmbaPioDevice(BasicPioDevice): 56 type = 'AmbaPioDevice' 57 abstract = True 58 cxx_header = "dev/arm/amba_device.hh" 59 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 60 61class AmbaIntDevice(AmbaPioDevice): 62 type = 'AmbaIntDevice' 63 abstract = True 64 cxx_header = "dev/arm/amba_device.hh" 65 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 66 int_num = Param.UInt32("Interrupt number that connects to GIC") 67 int_delay = Param.Latency("100ns", 68 "Time between action and interrupt generation by device") 69 70class AmbaDmaDevice(DmaDevice): 71 type = 'AmbaDmaDevice' 72 abstract = True 73 cxx_header = "dev/arm/amba_device.hh" 74 pio_addr = Param.Addr("Address for AMBA slave interface") 75 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 76 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 77 int_num = Param.UInt32("Interrupt number that connects to GIC") 78 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 79 80class A9SCU(BasicPioDevice): 81 type = 'A9SCU' 82 cxx_header = "dev/arm/a9scu.hh" 83 84class RealViewCtrl(BasicPioDevice): 85 type = 'RealViewCtrl' 86 cxx_header = "dev/arm/rv_ctrl.hh" 87 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 88 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 89 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 90 91class AmbaFake(AmbaPioDevice): 92 type = 'AmbaFake' 93 cxx_header = "dev/arm/amba_fake.hh" 94 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 95 amba_id = 0; 96 97class Pl011(Uart): 98 type = 'Pl011' 99 cxx_header = "dev/arm/pl011.hh" 100 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 101 int_num = Param.UInt32("Interrupt number that connects to GIC") 102 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 103 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 104 105class Sp804(AmbaPioDevice): 106 type = 'Sp804' 107 cxx_header = "dev/arm/timer_sp804.hh" 108 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 109 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 110 clock0 = Param.Clock('1MHz', "Clock speed of the input") 111 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 112 clock1 = Param.Clock('1MHz', "Clock speed of the input") 113 amba_id = 0x00141804 114 115class CpuLocalTimer(BasicPioDevice): 116 type = 'CpuLocalTimer' 117 cxx_header = "dev/arm/timer_cpulocal.hh" 118 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 119 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 120 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 121 122class PL031(AmbaIntDevice): 123 type = 'PL031' 124 cxx_header = "dev/arm/rtc_pl031.hh" 125 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 126 amba_id = 0x00341031 127 128class Pl050(AmbaIntDevice): 129 type = 'Pl050' 130 cxx_header = "dev/arm/kmi.hh" 131 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 132 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 133 int_delay = '1us' 134 amba_id = 0x00141050 135 136class Pl111(AmbaDmaDevice): 137 type = 'Pl111' 138 cxx_header = "dev/arm/pl111.hh" 139 pixel_clock = Param.Clock('24MHz', "Pixel clock") 140 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 141 amba_id = 0x00141111 142 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 143 144 145class HDLcd(AmbaDmaDevice): 146 type = 'HDLcd' 147 cxx_header = "dev/arm/hdlcd.hh" 148 pixel_clock = Param.Clock('65MHz', "Clock frequency of the pixel clock " 149 "(i.e. PXLREFCLK / OSCCLK 5; 23.75MHz " 150 "default up to 165MHz)") 151 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 152 "display") 153 amba_id = 0x00141000 154 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 155 156class RealView(Platform): 157 type = 'RealView' 158 cxx_header = "dev/arm/realview.hh" 159 system = Param.System(Parent.any, "system") 160 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 161 mem_start_addr = Param.Addr(0, "Start address of main memory") 162 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 163 164 def setupBootLoader(self, mem_bus, cur_sys, loc): 165 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 166 conf_table_reported = False) 167 self.nvmem.port = mem_bus.master 168 cur_sys.boot_loader = loc('boot.arm') 169 170 171# Reference for memory map and interrupt number 172# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 173# Chapter 4: Programmer's Reference 174class RealViewPBX(RealView): 175 uart = Pl011(pio_addr=0x10009000, int_num=44) 176 realview_io = RealViewCtrl(pio_addr=0x10000000) 177 gic = Pl390() 178 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 179 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 180 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 181 clcd = Pl111(pio_addr=0x10020000, int_num=55) 182 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 183 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 184 a9scu = A9SCU(pio_addr=0x1f000000) 185 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 186 io_shift = 1, ctrl_offset = 2, Command = 0x1, 187 BAR0 = 0x18000000, BAR0Size = '16B', 188 BAR1 = 0x18000100, BAR1Size = '1B', 189 BAR0LegacyIO = True, BAR1LegacyIO = True) 190 191 192 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 193 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 194 fake_mem=True) 195 dmac_fake = AmbaFake(pio_addr=0x10030000) 196 uart1_fake = AmbaFake(pio_addr=0x1000a000) 197 uart2_fake = AmbaFake(pio_addr=0x1000b000) 198 uart3_fake = AmbaFake(pio_addr=0x1000c000) 199 smc_fake = AmbaFake(pio_addr=0x100e1000) 200 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 201 watchdog_fake = AmbaFake(pio_addr=0x10010000) 202 gpio0_fake = AmbaFake(pio_addr=0x10013000) 203 gpio1_fake = AmbaFake(pio_addr=0x10014000) 204 gpio2_fake = AmbaFake(pio_addr=0x10015000) 205 ssp_fake = AmbaFake(pio_addr=0x1000d000) 206 sci_fake = AmbaFake(pio_addr=0x1000e000) 207 aaci_fake = AmbaFake(pio_addr=0x10004000) 208 mmc_fake = AmbaFake(pio_addr=0x10005000) 209 rtc = PL031(pio_addr=0x10017000, int_num=42) 210 211 212 # Attach I/O devices that are on chip and also set the appropriate 213 # ranges for the bridge 214 def attachOnChipIO(self, bus, bridge): 215 self.gic.pio = bus.master 216 self.l2x0_fake.pio = bus.master 217 self.a9scu.pio = bus.master 218 self.local_cpu_timer.pio = bus.master 219 # Bridge ranges based on excluding what is part of on-chip I/O 220 # (gic, l2x0, a9scu, local_cpu_timer) 221 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 222 self.a9scu.pio_addr - 1), 223 AddrRange(self.flash_fake.pio_addr, 224 self.flash_fake.pio_addr + \ 225 self.flash_fake.pio_size - 1)] 226 227 # Attach I/O devices to specified bus object. Can't do this 228 # earlier, since the bus object itself is typically defined at the 229 # System level. 230 def attachIO(self, bus): 231 self.uart.pio = bus.master 232 self.realview_io.pio = bus.master 233 self.timer0.pio = bus.master 234 self.timer1.pio = bus.master 235 self.clcd.pio = bus.master 236 self.clcd.dma = bus.slave 237 self.kmi0.pio = bus.master 238 self.kmi1.pio = bus.master 239 self.cf_ctrl.pio = bus.master 240 self.cf_ctrl.config = bus.master 241 self.cf_ctrl.dma = bus.slave 242 self.dmac_fake.pio = bus.master 243 self.uart1_fake.pio = bus.master 244 self.uart2_fake.pio = bus.master 245 self.uart3_fake.pio = bus.master 246 self.smc_fake.pio = bus.master 247 self.sp810_fake.pio = bus.master 248 self.watchdog_fake.pio = bus.master 249 self.gpio0_fake.pio = bus.master 250 self.gpio1_fake.pio = bus.master 251 self.gpio2_fake.pio = bus.master 252 self.ssp_fake.pio = bus.master 253 self.sci_fake.pio = bus.master 254 self.aaci_fake.pio = bus.master 255 self.mmc_fake.pio = bus.master 256 self.rtc.pio = bus.master 257 self.flash_fake.pio = bus.master 258 259# Reference for memory map and interrupt number 260# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 261# Chapter 4: Programmer's Reference 262class RealViewEB(RealView): 263 uart = Pl011(pio_addr=0x10009000, int_num=44) 264 realview_io = RealViewCtrl(pio_addr=0x10000000) 265 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 266 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 267 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 268 clcd = Pl111(pio_addr=0x10020000, int_num=23) 269 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 270 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 271 272 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 273 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 274 fake_mem=True) 275 dmac_fake = AmbaFake(pio_addr=0x10030000) 276 uart1_fake = AmbaFake(pio_addr=0x1000a000) 277 uart2_fake = AmbaFake(pio_addr=0x1000b000) 278 uart3_fake = AmbaFake(pio_addr=0x1000c000) 279 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 280 smc_fake = AmbaFake(pio_addr=0x100e1000) 281 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 282 watchdog_fake = AmbaFake(pio_addr=0x10010000) 283 gpio0_fake = AmbaFake(pio_addr=0x10013000) 284 gpio1_fake = AmbaFake(pio_addr=0x10014000) 285 gpio2_fake = AmbaFake(pio_addr=0x10015000) 286 ssp_fake = AmbaFake(pio_addr=0x1000d000) 287 sci_fake = AmbaFake(pio_addr=0x1000e000) 288 aaci_fake = AmbaFake(pio_addr=0x10004000) 289 mmc_fake = AmbaFake(pio_addr=0x10005000) 290 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 291 292 293 294 # Attach I/O devices that are on chip and also set the appropriate 295 # ranges for the bridge 296 def attachOnChipIO(self, bus, bridge): 297 self.gic.pio = bus.master 298 self.l2x0_fake.pio = bus.master 299 # Bridge ranges based on excluding what is part of on-chip I/O 300 # (gic, l2x0) 301 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 302 self.gic.cpu_addr - 1), 303 AddrRange(self.flash_fake.pio_addr, Addr.max)] 304 305 # Attach I/O devices to specified bus object. Can't do this 306 # earlier, since the bus object itself is typically defined at the 307 # System level. 308 def attachIO(self, bus): 309 self.uart.pio = bus.master 310 self.realview_io.pio = bus.master 311 self.timer0.pio = bus.master 312 self.timer1.pio = bus.master 313 self.clcd.pio = bus.master 314 self.clcd.dma = bus.slave 315 self.kmi0.pio = bus.master 316 self.kmi1.pio = bus.master 317 self.dmac_fake.pio = bus.master 318 self.uart1_fake.pio = bus.master 319 self.uart2_fake.pio = bus.master 320 self.uart3_fake.pio = bus.master 321 self.smc_fake.pio = bus.master 322 self.sp810_fake.pio = bus.master 323 self.watchdog_fake.pio = bus.master 324 self.gpio0_fake.pio = bus.master 325 self.gpio1_fake.pio = bus.master 326 self.gpio2_fake.pio = bus.master 327 self.ssp_fake.pio = bus.master 328 self.sci_fake.pio = bus.master 329 self.aaci_fake.pio = bus.master 330 self.mmc_fake.pio = bus.master 331 self.rtc_fake.pio = bus.master 332 self.flash_fake.pio = bus.master 333 self.smcreg_fake.pio = bus.master 334 335class VExpress_EMM(RealView): 336 mem_start_addr = '2GB' 337 max_mem_size = '2GB' 338 pci_cfg_base = 0x30000000 339 uart = Pl011(pio_addr=0x1c090000, int_num=37) 340 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 341 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 342 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 343 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 344 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 345 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 346 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 347 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 348 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 349 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 350 io_shift = 2, ctrl_offset = 2, Command = 0x1, 351 BAR0 = 0x1C1A0000, BAR0Size = '256B', 352 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 353 BAR0LegacyIO = True, BAR1LegacyIO = True) 354 355 pciconfig = PciConfigAll(size='256MB') 356 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 357 InterruptLine=1, InterruptPin=1) 358 359 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 360 InterruptLine=2, InterruptPin=2) 361 362 363 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 364 conf_table_reported = False) 365 rtc = PL031(pio_addr=0x1C170000, int_num=36) 366 367 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 368 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 369 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 370 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 371 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 372 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 373 aaci_fake = AmbaFake(pio_addr=0x1C040000) 374 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 375 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 376 mmc_fake = AmbaFake(pio_addr=0x1c050000) 377 378 def setupBootLoader(self, mem_bus, cur_sys, loc): 379 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 380 conf_table_reported = False) 381 self.nvmem.port = mem_bus.master 382 cur_sys.boot_loader = loc('boot_emm.arm') 383 cur_sys.atags_addr = 0x80000100 384 385 # Attach I/O devices that are on chip and also set the appropriate 386 # ranges for the bridge 387 def attachOnChipIO(self, bus, bridge): 388 self.gic.pio = bus.master 389 self.local_cpu_timer.pio = bus.master 390 self.hdlcd.dma = bus.slave 391 # Bridge ranges based on excluding what is part of on-chip I/O 392 # (gic, a9scu) 393 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 394 AddrRange(0x2B000000, size='4MB'), 395 AddrRange(0x30000000, size='256MB'), 396 AddrRange(0x40000000, size='512MB'), 397 AddrRange(0x18000000, size='64MB'), 398 AddrRange(0x1C000000, size='64MB')] 399 400 # Attach I/O devices to specified bus object. Can't do this 401 # earlier, since the bus object itself is typically defined at the 402 # System level. 403 def attachIO(self, bus): 404 self.uart.pio = bus.master 405 self.realview_io.pio = bus.master 406 self.timer0.pio = bus.master 407 self.timer1.pio = bus.master 408 self.clcd.pio = bus.master 409 self.clcd.dma = bus.slave 410 self.hdlcd.pio = bus.master 411 self.kmi0.pio = bus.master 412 self.kmi1.pio = bus.master 413 self.cf_ctrl.pio = bus.master 414 self.cf_ctrl.dma = bus.slave 415 self.cf_ctrl.config = bus.master 416 self.rtc.pio = bus.master 417 bus.use_default_range = True 418 self.vram.port = bus.master 419 self.ide.pio = bus.master 420 self.ide.config = bus.master 421 self.ide.dma = bus.slave 422 self.ethernet.pio = bus.master 423 self.ethernet.config = bus.master 424 self.ethernet.dma = bus.slave 425 self.pciconfig.pio = bus.default 426 427 self.l2x0_fake.pio = bus.master 428 self.uart1_fake.pio = bus.master 429 self.uart2_fake.pio = bus.master 430 self.uart3_fake.pio = bus.master 431 self.sp810_fake.pio = bus.master 432 self.watchdog_fake.pio = bus.master 433 self.aaci_fake.pio = bus.master 434 self.lan_fake.pio = bus.master 435 self.usb_fake.pio = bus.master 436 self.mmc_fake.pio = bus.master 437 438