RealView.py revision 9073:f75ee4849c40
1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53 54class AmbaDevice(BasicPioDevice): 55 type = 'AmbaDevice' 56 abstract = True 57 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 58 59class AmbaIntDevice(AmbaDevice): 60 type = 'AmbaIntDevice' 61 abstract = True 62 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 63 int_num = Param.UInt32("Interrupt number that connects to GIC") 64 int_delay = Param.Latency("100ns", 65 "Time between action and interrupt generation by device") 66 67class AmbaDmaDevice(DmaDevice): 68 type = 'AmbaDmaDevice' 69 abstract = True 70 pio_addr = Param.Addr("Address for AMBA slave interface") 71 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 72 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 73 int_num = Param.UInt32("Interrupt number that connects to GIC") 74 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 75 76class A9SCU(BasicPioDevice): 77 type = 'A9SCU' 78 79class RealViewCtrl(BasicPioDevice): 80 type = 'RealViewCtrl' 81 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 82 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 83 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 84 85class Gic(PioDevice): 86 type = 'Gic' 87 platform = Param.Platform(Parent.any, "Platform this device is part of.") 88 dist_addr = Param.Addr(0x1f001000, "Address for distributor") 89 cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 90 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 91 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 92 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 93 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 94 95class AmbaFake(AmbaDevice): 96 type = 'AmbaFake' 97 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 98 amba_id = 0; 99 100class Pl011(Uart): 101 type = 'Pl011' 102 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 103 int_num = Param.UInt32("Interrupt number that connects to GIC") 104 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 105 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 106 107class Sp804(AmbaDevice): 108 type = 'Sp804' 109 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 110 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 111 clock0 = Param.Clock('1MHz', "Clock speed of the input") 112 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 113 clock1 = Param.Clock('1MHz', "Clock speed of the input") 114 amba_id = 0x00141804 115 116class CpuLocalTimer(BasicPioDevice): 117 type = 'CpuLocalTimer' 118 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 119 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 120 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 121 clock = Param.Clock('1GHz', "Clock speed at which the timer counts") 122 123class PL031(AmbaIntDevice): 124 type = 'PL031' 125 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 126 amba_id = 0x00341031 127 128class Pl050(AmbaIntDevice): 129 type = 'Pl050' 130 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 131 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 132 int_delay = '1us' 133 amba_id = 0x00141050 134 135class Pl111(AmbaDmaDevice): 136 type = 'Pl111' 137 clock = Param.Clock('24MHz', "Clock speed of the input") 138 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 139 amba_id = 0x00141111 140 141class RealView(Platform): 142 type = 'RealView' 143 system = Param.System(Parent.any, "system") 144 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 145 mem_start_addr = Param.Addr(0, "Start address of main memory") 146 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 147 148 def setupBootLoader(self, mem_bus, cur_sys, loc): 149 self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), 150 size = '64MB'), 151 zero = True) 152 self.nvmem.port = mem_bus.master 153 cur_sys.boot_loader = loc('boot.arm') 154 155 156# Reference for memory map and interrupt number 157# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 158# Chapter 4: Programmer's Reference 159class RealViewPBX(RealView): 160 uart = Pl011(pio_addr=0x10009000, int_num=44) 161 realview_io = RealViewCtrl(pio_addr=0x10000000) 162 gic = Gic() 163 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 164 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 165 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 166 clcd = Pl111(pio_addr=0x10020000, int_num=55) 167 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 168 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 169 a9scu = A9SCU(pio_addr=0x1f000000) 170 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 171 io_shift = 1, ctrl_offset = 2, Command = 0x1, 172 BAR0 = 0x18000000, BAR0Size = '16B', 173 BAR1 = 0x18000100, BAR1Size = '1B', 174 BAR0LegacyIO = True, BAR1LegacyIO = True) 175 176 177 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 178 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 179 fake_mem=True) 180 dmac_fake = AmbaFake(pio_addr=0x10030000) 181 uart1_fake = AmbaFake(pio_addr=0x1000a000) 182 uart2_fake = AmbaFake(pio_addr=0x1000b000) 183 uart3_fake = AmbaFake(pio_addr=0x1000c000) 184 smc_fake = AmbaFake(pio_addr=0x100e1000) 185 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 186 watchdog_fake = AmbaFake(pio_addr=0x10010000) 187 gpio0_fake = AmbaFake(pio_addr=0x10013000) 188 gpio1_fake = AmbaFake(pio_addr=0x10014000) 189 gpio2_fake = AmbaFake(pio_addr=0x10015000) 190 ssp_fake = AmbaFake(pio_addr=0x1000d000) 191 sci_fake = AmbaFake(pio_addr=0x1000e000) 192 aaci_fake = AmbaFake(pio_addr=0x10004000) 193 mmc_fake = AmbaFake(pio_addr=0x10005000) 194 rtc = PL031(pio_addr=0x10017000, int_num=42) 195 196 197 # Attach I/O devices that are on chip and also set the appropriate 198 # ranges for the bridge 199 def attachOnChipIO(self, bus, bridge): 200 self.gic.pio = bus.master 201 self.l2x0_fake.pio = bus.master 202 self.a9scu.pio = bus.master 203 self.local_cpu_timer.pio = bus.master 204 # Bridge ranges based on excluding what is part of on-chip I/O 205 # (gic, l2x0, a9scu, local_cpu_timer) 206 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 207 self.a9scu.pio_addr - 1), 208 AddrRange(self.flash_fake.pio_addr, 209 self.flash_fake.pio_addr + \ 210 self.flash_fake.pio_size - 1)] 211 212 # Attach I/O devices to specified bus object. Can't do this 213 # earlier, since the bus object itself is typically defined at the 214 # System level. 215 def attachIO(self, bus): 216 self.uart.pio = bus.master 217 self.realview_io.pio = bus.master 218 self.timer0.pio = bus.master 219 self.timer1.pio = bus.master 220 self.clcd.pio = bus.master 221 self.clcd.dma = bus.slave 222 self.kmi0.pio = bus.master 223 self.kmi1.pio = bus.master 224 self.cf_ctrl.pio = bus.master 225 self.cf_ctrl.config = bus.master 226 self.cf_ctrl.dma = bus.slave 227 self.dmac_fake.pio = bus.master 228 self.uart1_fake.pio = bus.master 229 self.uart2_fake.pio = bus.master 230 self.uart3_fake.pio = bus.master 231 self.smc_fake.pio = bus.master 232 self.sp810_fake.pio = bus.master 233 self.watchdog_fake.pio = bus.master 234 self.gpio0_fake.pio = bus.master 235 self.gpio1_fake.pio = bus.master 236 self.gpio2_fake.pio = bus.master 237 self.ssp_fake.pio = bus.master 238 self.sci_fake.pio = bus.master 239 self.aaci_fake.pio = bus.master 240 self.mmc_fake.pio = bus.master 241 self.rtc.pio = bus.master 242 self.flash_fake.pio = bus.master 243 244# Reference for memory map and interrupt number 245# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 246# Chapter 4: Programmer's Reference 247class RealViewEB(RealView): 248 uart = Pl011(pio_addr=0x10009000, int_num=44) 249 realview_io = RealViewCtrl(pio_addr=0x10000000) 250 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 251 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 252 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 253 clcd = Pl111(pio_addr=0x10020000, int_num=23) 254 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 255 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 256 257 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 258 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 259 fake_mem=True) 260 dmac_fake = AmbaFake(pio_addr=0x10030000) 261 uart1_fake = AmbaFake(pio_addr=0x1000a000) 262 uart2_fake = AmbaFake(pio_addr=0x1000b000) 263 uart3_fake = AmbaFake(pio_addr=0x1000c000) 264 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 265 smc_fake = AmbaFake(pio_addr=0x100e1000) 266 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 267 watchdog_fake = AmbaFake(pio_addr=0x10010000) 268 gpio0_fake = AmbaFake(pio_addr=0x10013000) 269 gpio1_fake = AmbaFake(pio_addr=0x10014000) 270 gpio2_fake = AmbaFake(pio_addr=0x10015000) 271 ssp_fake = AmbaFake(pio_addr=0x1000d000) 272 sci_fake = AmbaFake(pio_addr=0x1000e000) 273 aaci_fake = AmbaFake(pio_addr=0x10004000) 274 mmc_fake = AmbaFake(pio_addr=0x10005000) 275 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 276 277 278 279 # Attach I/O devices that are on chip and also set the appropriate 280 # ranges for the bridge 281 def attachOnChipIO(self, bus, bridge): 282 self.gic.pio = bus.master 283 self.l2x0_fake.pio = bus.master 284 # Bridge ranges based on excluding what is part of on-chip I/O 285 # (gic, l2x0) 286 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 287 self.gic.cpu_addr - 1), 288 AddrRange(self.flash_fake.pio_addr, Addr.max)] 289 290 # Attach I/O devices to specified bus object. Can't do this 291 # earlier, since the bus object itself is typically defined at the 292 # System level. 293 def attachIO(self, bus): 294 self.uart.pio = bus.master 295 self.realview_io.pio = bus.master 296 self.timer0.pio = bus.master 297 self.timer1.pio = bus.master 298 self.clcd.pio = bus.master 299 self.clcd.dma = bus.slave 300 self.kmi0.pio = bus.master 301 self.kmi1.pio = bus.master 302 self.dmac_fake.pio = bus.master 303 self.uart1_fake.pio = bus.master 304 self.uart2_fake.pio = bus.master 305 self.uart3_fake.pio = bus.master 306 self.smc_fake.pio = bus.master 307 self.sp810_fake.pio = bus.master 308 self.watchdog_fake.pio = bus.master 309 self.gpio0_fake.pio = bus.master 310 self.gpio1_fake.pio = bus.master 311 self.gpio2_fake.pio = bus.master 312 self.ssp_fake.pio = bus.master 313 self.sci_fake.pio = bus.master 314 self.aaci_fake.pio = bus.master 315 self.mmc_fake.pio = bus.master 316 self.rtc_fake.pio = bus.master 317 self.flash_fake.pio = bus.master 318 self.smcreg_fake.pio = bus.master 319 320class VExpress_EMM(RealView): 321 mem_start_addr = '2GB' 322 max_mem_size = '2GB' 323 pci_cfg_base = 0x30000000 324 uart = Pl011(pio_addr=0x1c090000, int_num=37) 325 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 326 gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000) 327 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 328 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='50MHz', clock1='50MHz') 329 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='50MHz', clock1='50MHz') 330 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 331 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 332 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45) 333 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 334 io_shift = 2, ctrl_offset = 2, Command = 0x1, 335 BAR0 = 0x1C1A0000, BAR0Size = '256B', 336 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 337 BAR0LegacyIO = True, BAR1LegacyIO = True) 338 339 pciconfig = PciConfigAll(size='256MB') 340 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 341 InterruptLine=1, InterruptPin=1) 342 343 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 344 InterruptLine=2, InterruptPin=2) 345 346 347 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 348 zero = True) 349 rtc = PL031(pio_addr=0x1C170000, int_num=36) 350 351 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 352 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 353 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 354 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 355 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 356 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 357 aaci_fake = AmbaFake(pio_addr=0x1C040000) 358 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 359 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 360 mmc_fake = AmbaFake(pio_addr=0x1c050000) 361 362 def setupBootLoader(self, mem_bus, cur_sys, loc): 363 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'), 364 zero = True) 365 self.nvmem.port = mem_bus.master 366 cur_sys.boot_loader = loc('boot_emm.arm') 367 cur_sys.atags_addr = 0x80000100 368 369 # Attach I/O devices that are on chip and also set the appropriate 370 # ranges for the bridge 371 def attachOnChipIO(self, bus, bridge): 372 self.gic.pio = bus.master 373 self.local_cpu_timer.pio = bus.master 374 # Bridge ranges based on excluding what is part of on-chip I/O 375 # (gic, a9scu) 376 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 377 AddrRange(0x30000000, size='256MB'), 378 AddrRange(0x40000000, size='512MB'), 379 AddrRange(0x18000000, size='64MB'), 380 AddrRange(0x1C000000, size='64MB')] 381 382 # Attach I/O devices to specified bus object. Can't do this 383 # earlier, since the bus object itself is typically defined at the 384 # System level. 385 def attachIO(self, bus): 386 self.uart.pio = bus.master 387 self.realview_io.pio = bus.master 388 self.timer0.pio = bus.master 389 self.timer1.pio = bus.master 390 self.clcd.pio = bus.master 391 self.clcd.dma = bus.slave 392 self.kmi0.pio = bus.master 393 self.kmi1.pio = bus.master 394 self.cf_ctrl.pio = bus.master 395 self.cf_ctrl.dma = bus.slave 396 self.cf_ctrl.config = bus.master 397 self.rtc.pio = bus.master 398 bus.use_default_range = True 399 self.vram.port = bus.master 400 self.ide.pio = bus.master 401 self.ide.config = bus.master 402 self.ide.dma = bus.slave 403 self.ethernet.pio = bus.master 404 self.ethernet.config = bus.master 405 self.ethernet.dma = bus.slave 406 self.pciconfig.pio = bus.default 407 408 self.l2x0_fake.pio = bus.master 409 self.uart1_fake.pio = bus.master 410 self.uart2_fake.pio = bus.master 411 self.uart3_fake.pio = bus.master 412 self.sp810_fake.pio = bus.master 413 self.watchdog_fake.pio = bus.master 414 self.aaci_fake.pio = bus.master 415 self.lan_fake.pio = bus.master 416 self.usb_fake.pio = bus.master 417 self.mmc_fake.pio = bus.master 418 419