RealView.py revision 11090:f37a6b82f98f
1# Copyright (c) 2009-2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from ClockDomain import ClockDomain 46from VoltageDomain import VoltageDomain 47from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 48from Pci import PciConfigAll 49from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 50from Ide import * 51from Platform import Platform 52from Terminal import Terminal 53from Uart import Uart 54from SimpleMemory import SimpleMemory 55from Gic import * 56from EnergyCtrl import EnergyCtrl 57from ClockDomain import SrcClockDomain 58 59class AmbaPioDevice(BasicPioDevice): 60 type = 'AmbaPioDevice' 61 abstract = True 62 cxx_header = "dev/arm/amba_device.hh" 63 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 64 65class AmbaIntDevice(AmbaPioDevice): 66 type = 'AmbaIntDevice' 67 abstract = True 68 cxx_header = "dev/arm/amba_device.hh" 69 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 70 int_num = Param.UInt32("Interrupt number that connects to GIC") 71 int_delay = Param.Latency("100ns", 72 "Time between action and interrupt generation by device") 73 74class AmbaDmaDevice(DmaDevice): 75 type = 'AmbaDmaDevice' 76 abstract = True 77 cxx_header = "dev/arm/amba_device.hh" 78 pio_addr = Param.Addr("Address for AMBA slave interface") 79 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 80 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 81 int_num = Param.UInt32("Interrupt number that connects to GIC") 82 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 83 84class A9SCU(BasicPioDevice): 85 type = 'A9SCU' 86 cxx_header = "dev/arm/a9scu.hh" 87 88class RealViewCtrl(BasicPioDevice): 89 type = 'RealViewCtrl' 90 cxx_header = "dev/arm/rv_ctrl.hh" 91 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 92 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 93 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 94 95class RealViewOsc(ClockDomain): 96 type = 'RealViewOsc' 97 cxx_header = "dev/arm/rv_ctrl.hh" 98 99 parent = Param.RealViewCtrl(Parent.any, "RealView controller") 100 101 # TODO: We currently don't have the notion of a clock source, 102 # which means we have to associate oscillators with a voltage 103 # source. 104 voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 105 "Voltage domain") 106 107 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 108 # the individual core/logic tile reference manuals for details 109 # about the site/position/dcc/device allocation. 110 site = Param.UInt8("Board Site") 111 position = Param.UInt8("Position in device stack") 112 dcc = Param.UInt8("Daughterboard Configuration Controller") 113 device = Param.UInt8("Device ID") 114 115 freq = Param.Clock("Default frequency") 116 117class VExpressCoreTileCtrl(RealViewCtrl): 118 class MotherBoardOsc(RealViewOsc): 119 site, position, dcc = (0, 0, 0) 120 121 class CoreTileOsc(RealViewOsc): 122 site, position, dcc = (1, 0, 0) 123 124 # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) 125 osc_mcc = MotherBoardOsc(device=0, freq="50MHz") 126 osc_clcd = MotherBoardOsc(device=1, freq="23.75MHz") 127 osc_peripheral = MotherBoardOsc(device=2, freq="24MHz") 128 osc_system_bus = MotherBoardOsc(device=4, freq="24MHz") 129 130 # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM). 131 osc_cpu = CoreTileOsc(device=0, freq="60MHz") 132 osc_hsbm = CoreTileOsc(device=4, freq="40MHz") 133 osc_pxl = CoreTileOsc(device=5, freq="23.75MHz") 134 osc_smb = CoreTileOsc(device=6, freq="50MHz") 135 osc_sys = CoreTileOsc(device=7, freq="60MHz") 136 osc_ddr = CoreTileOsc(device=8, freq="40MHz") 137 138class VGic(PioDevice): 139 type = 'VGic' 140 cxx_header = "dev/arm/vgic.hh" 141 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 142 platform = Param.Platform(Parent.any, "Platform this device is part of.") 143 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 144 hv_addr = Param.Addr(0, "Address for hv control") 145 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 146 # The number of list registers is not currently configurable at runtime. 147 ppint = Param.UInt32("HV maintenance interrupt number") 148 149class AmbaFake(AmbaPioDevice): 150 type = 'AmbaFake' 151 cxx_header = "dev/arm/amba_fake.hh" 152 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 153 amba_id = 0; 154 155class Pl011(Uart): 156 type = 'Pl011' 157 cxx_header = "dev/arm/pl011.hh" 158 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 159 int_num = Param.UInt32("Interrupt number that connects to GIC") 160 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 161 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 162 163class Sp804(AmbaPioDevice): 164 type = 'Sp804' 165 cxx_header = "dev/arm/timer_sp804.hh" 166 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 167 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 168 clock0 = Param.Clock('1MHz', "Clock speed of the input") 169 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 170 clock1 = Param.Clock('1MHz', "Clock speed of the input") 171 amba_id = 0x00141804 172 173class CpuLocalTimer(BasicPioDevice): 174 type = 'CpuLocalTimer' 175 cxx_header = "dev/arm/timer_cpulocal.hh" 176 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 177 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 178 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 179 180class GenericTimer(SimObject): 181 type = 'GenericTimer' 182 cxx_header = "dev/arm/generic_timer.hh" 183 system = Param.System(Parent.any, "system") 184 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 185 # @todo: for now only two timers per CPU is supported, which is the 186 # normal behaviour when security extensions are disabled. 187 int_phys = Param.UInt32("Physical timer interrupt number") 188 int_virt = Param.UInt32("Virtual timer interrupt number") 189 190class GenericTimerMem(PioDevice): 191 type = 'GenericTimerMem' 192 cxx_header = "dev/arm/generic_timer.hh" 193 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 194 195 base = Param.Addr(0, "Base address") 196 197 int_phys = Param.UInt32("Interrupt number") 198 int_virt = Param.UInt32("Interrupt number") 199 200class PL031(AmbaIntDevice): 201 type = 'PL031' 202 cxx_header = "dev/arm/rtc_pl031.hh" 203 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 204 amba_id = 0x00341031 205 206class Pl050(AmbaIntDevice): 207 type = 'Pl050' 208 cxx_header = "dev/arm/kmi.hh" 209 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 210 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 211 int_delay = '1us' 212 amba_id = 0x00141050 213 214class Pl111(AmbaDmaDevice): 215 type = 'Pl111' 216 cxx_header = "dev/arm/pl111.hh" 217 pixel_clock = Param.Clock('24MHz', "Pixel clock") 218 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 219 amba_id = 0x00141111 220 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 221 222class HDLcd(AmbaDmaDevice): 223 type = 'HDLcd' 224 cxx_header = "dev/arm/hdlcd.hh" 225 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 226 "display") 227 amba_id = 0x00141000 228 workaround_swap_rb = Param.Bool(True, "Workaround incorrect color " 229 "selector order in some kernels") 230 workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 231 "DMA line count (off by 1)") 232 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 233 234 pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 235 236 pxl_clk = Param.ClockDomain("Pixel clock source") 237 pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 238 239class RealView(Platform): 240 type = 'RealView' 241 cxx_header = "dev/arm/realview.hh" 242 system = Param.System(Parent.any, "system") 243 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 244 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 245 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 246 " be compatible with the pci-generic-host or the legacy host bridge?") 247 _mem_regions = [(Addr(0), Addr('256MB'))] 248 249 def attachPciDevices(self): 250 pass 251 252 def enableMSIX(self): 253 pass 254 255 def onChipIOClkDomain(self, clkdomain): 256 pass 257 258 def offChipIOClkDomain(self, clkdomain): 259 pass 260 261 def setupBootLoader(self, mem_bus, cur_sys, loc): 262 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 263 conf_table_reported = False) 264 self.nvmem.port = mem_bus.master 265 cur_sys.boot_loader = loc('boot.arm') 266 cur_sys.atags_addr = 0x100 267 cur_sys.load_addr_mask = 0xfffffff 268 cur_sys.load_offset = 0 269 270 271# Reference for memory map and interrupt number 272# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 273# Chapter 4: Programmer's Reference 274class RealViewPBX(RealView): 275 uart = Pl011(pio_addr=0x10009000, int_num=44) 276 realview_io = VExpressCoreTileCtrl(pio_addr=0x10000000) 277 gic = Pl390() 278 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 279 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 280 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 281 clcd = Pl111(pio_addr=0x10020000, int_num=55) 282 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 283 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 284 a9scu = A9SCU(pio_addr=0x1f000000) 285 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 286 io_shift = 1, ctrl_offset = 2, Command = 0x1, 287 BAR0 = 0x18000000, BAR0Size = '16B', 288 BAR1 = 0x18000100, BAR1Size = '1B', 289 BAR0LegacyIO = True, BAR1LegacyIO = True) 290 291 292 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 293 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 294 fake_mem=True) 295 dmac_fake = AmbaFake(pio_addr=0x10030000) 296 uart1_fake = AmbaFake(pio_addr=0x1000a000) 297 uart2_fake = AmbaFake(pio_addr=0x1000b000) 298 uart3_fake = AmbaFake(pio_addr=0x1000c000) 299 smc_fake = AmbaFake(pio_addr=0x100e1000) 300 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 301 watchdog_fake = AmbaFake(pio_addr=0x10010000) 302 gpio0_fake = AmbaFake(pio_addr=0x10013000) 303 gpio1_fake = AmbaFake(pio_addr=0x10014000) 304 gpio2_fake = AmbaFake(pio_addr=0x10015000) 305 ssp_fake = AmbaFake(pio_addr=0x1000d000) 306 sci_fake = AmbaFake(pio_addr=0x1000e000) 307 aaci_fake = AmbaFake(pio_addr=0x10004000) 308 mmc_fake = AmbaFake(pio_addr=0x10005000) 309 rtc = PL031(pio_addr=0x10017000, int_num=42) 310 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 311 312 313 # Attach I/O devices that are on chip and also set the appropriate 314 # ranges for the bridge 315 def attachOnChipIO(self, bus, bridge): 316 self.gic.pio = bus.master 317 self.l2x0_fake.pio = bus.master 318 self.a9scu.pio = bus.master 319 self.local_cpu_timer.pio = bus.master 320 # Bridge ranges based on excluding what is part of on-chip I/O 321 # (gic, l2x0, a9scu, local_cpu_timer) 322 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 323 self.a9scu.pio_addr - 1), 324 AddrRange(self.flash_fake.pio_addr, 325 self.flash_fake.pio_addr + \ 326 self.flash_fake.pio_size - 1)] 327 328 # Set the clock domain for IO objects that are considered 329 # to be "close" to the cores. 330 def onChipIOClkDomain(self, clkdomain): 331 self.gic.clk_domain = clkdomain 332 self.l2x0_fake.clk_domain = clkdomain 333 self.a9scu.clkdomain = clkdomain 334 self.local_cpu_timer.clk_domain = clkdomain 335 336 # Attach I/O devices to specified bus object. Can't do this 337 # earlier, since the bus object itself is typically defined at the 338 # System level. 339 def attachIO(self, bus): 340 self.uart.pio = bus.master 341 self.realview_io.pio = bus.master 342 self.timer0.pio = bus.master 343 self.timer1.pio = bus.master 344 self.clcd.pio = bus.master 345 self.clcd.dma = bus.slave 346 self.kmi0.pio = bus.master 347 self.kmi1.pio = bus.master 348 self.cf_ctrl.pio = bus.master 349 self.cf_ctrl.config = bus.master 350 self.cf_ctrl.dma = bus.slave 351 self.dmac_fake.pio = bus.master 352 self.uart1_fake.pio = bus.master 353 self.uart2_fake.pio = bus.master 354 self.uart3_fake.pio = bus.master 355 self.smc_fake.pio = bus.master 356 self.sp810_fake.pio = bus.master 357 self.watchdog_fake.pio = bus.master 358 self.gpio0_fake.pio = bus.master 359 self.gpio1_fake.pio = bus.master 360 self.gpio2_fake.pio = bus.master 361 self.ssp_fake.pio = bus.master 362 self.sci_fake.pio = bus.master 363 self.aaci_fake.pio = bus.master 364 self.mmc_fake.pio = bus.master 365 self.rtc.pio = bus.master 366 self.flash_fake.pio = bus.master 367 self.energy_ctrl.pio = bus.master 368 369 # Set the clock domain for IO objects that are considered 370 # to be "far" away from the cores. 371 def offChipIOClkDomain(self, clkdomain): 372 self.uart.clk_domain = clkdomain 373 self.realview_io.clk_domain = clkdomain 374 self.timer0.clk_domain = clkdomain 375 self.timer1.clk_domain = clkdomain 376 self.clcd.clk_domain = clkdomain 377 self.kmi0.clk_domain = clkdomain 378 self.kmi1.clk_domain = clkdomain 379 self.cf_ctrl.clk_domain = clkdomain 380 self.dmac_fake.clk_domain = clkdomain 381 self.uart1_fake.clk_domain = clkdomain 382 self.uart2_fake.clk_domain = clkdomain 383 self.uart3_fake.clk_domain = clkdomain 384 self.smc_fake.clk_domain = clkdomain 385 self.sp810_fake.clk_domain = clkdomain 386 self.watchdog_fake.clk_domain = clkdomain 387 self.gpio0_fake.clk_domain = clkdomain 388 self.gpio1_fake.clk_domain = clkdomain 389 self.gpio2_fake.clk_domain = clkdomain 390 self.ssp_fake.clk_domain = clkdomain 391 self.sci_fake.clk_domain = clkdomain 392 self.aaci_fake.clk_domain = clkdomain 393 self.mmc_fake.clk_domain = clkdomain 394 self.rtc.clk_domain = clkdomain 395 self.flash_fake.clk_domain = clkdomain 396 self.energy_ctrl.clk_domain = clkdomain 397 398# Reference for memory map and interrupt number 399# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 400# Chapter 4: Programmer's Reference 401class RealViewEB(RealView): 402 uart = Pl011(pio_addr=0x10009000, int_num=44) 403 realview_io = VExpressCoreTileCtrl(pio_addr=0x10000000, idreg=0x01400500) 404 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 405 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 406 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 407 clcd = Pl111(pio_addr=0x10020000, int_num=23) 408 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 409 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 410 411 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 412 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 413 fake_mem=True) 414 dmac_fake = AmbaFake(pio_addr=0x10030000) 415 uart1_fake = AmbaFake(pio_addr=0x1000a000) 416 uart2_fake = AmbaFake(pio_addr=0x1000b000) 417 uart3_fake = AmbaFake(pio_addr=0x1000c000) 418 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 419 smc_fake = AmbaFake(pio_addr=0x100e1000) 420 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 421 watchdog_fake = AmbaFake(pio_addr=0x10010000) 422 gpio0_fake = AmbaFake(pio_addr=0x10013000) 423 gpio1_fake = AmbaFake(pio_addr=0x10014000) 424 gpio2_fake = AmbaFake(pio_addr=0x10015000) 425 ssp_fake = AmbaFake(pio_addr=0x1000d000) 426 sci_fake = AmbaFake(pio_addr=0x1000e000) 427 aaci_fake = AmbaFake(pio_addr=0x10004000) 428 mmc_fake = AmbaFake(pio_addr=0x10005000) 429 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 430 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 431 432 # Attach I/O devices that are on chip and also set the appropriate 433 # ranges for the bridge 434 def attachOnChipIO(self, bus, bridge): 435 self.gic.pio = bus.master 436 self.l2x0_fake.pio = bus.master 437 # Bridge ranges based on excluding what is part of on-chip I/O 438 # (gic, l2x0) 439 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 440 self.gic.cpu_addr - 1), 441 AddrRange(self.flash_fake.pio_addr, Addr.max)] 442 443 # Set the clock domain for IO objects that are considered 444 # to be "close" to the cores. 445 def onChipIOClkDomain(self, clkdomain): 446 self.gic.clk_domain = clkdomain 447 self.l2x0_fake.clk_domain = clkdomain 448 449 # Attach I/O devices to specified bus object. Can't do this 450 # earlier, since the bus object itself is typically defined at the 451 # System level. 452 def attachIO(self, bus): 453 self.uart.pio = bus.master 454 self.realview_io.pio = bus.master 455 self.timer0.pio = bus.master 456 self.timer1.pio = bus.master 457 self.clcd.pio = bus.master 458 self.clcd.dma = bus.slave 459 self.kmi0.pio = bus.master 460 self.kmi1.pio = bus.master 461 self.dmac_fake.pio = bus.master 462 self.uart1_fake.pio = bus.master 463 self.uart2_fake.pio = bus.master 464 self.uart3_fake.pio = bus.master 465 self.smc_fake.pio = bus.master 466 self.sp810_fake.pio = bus.master 467 self.watchdog_fake.pio = bus.master 468 self.gpio0_fake.pio = bus.master 469 self.gpio1_fake.pio = bus.master 470 self.gpio2_fake.pio = bus.master 471 self.ssp_fake.pio = bus.master 472 self.sci_fake.pio = bus.master 473 self.aaci_fake.pio = bus.master 474 self.mmc_fake.pio = bus.master 475 self.rtc_fake.pio = bus.master 476 self.flash_fake.pio = bus.master 477 self.smcreg_fake.pio = bus.master 478 self.energy_ctrl.pio = bus.master 479 480 # Set the clock domain for IO objects that are considered 481 # to be "far" away from the cores. 482 def offChipIOClkDomain(self, clkdomain): 483 self.uart.clk_domain = clkdomain 484 self.realview_io.clk_domain = clkdomain 485 self.timer0.clk_domain = clkdomain 486 self.timer1.clk_domain = clkdomain 487 self.clcd.clk_domain = clkdomain 488 self.kmi0.clk_domain = clkdomain 489 self.kmi1.clk_domain = clkdomain 490 self.dmac_fake.clk_domain = clkdomain 491 self.uart1_fake.clk_domain = clkdomain 492 self.uart2_fake.clk_domain = clkdomain 493 self.uart3_fake.clk_domain = clkdomain 494 self.smc_fake.clk_domain = clkdomain 495 self.sp810_fake.clk_domain = clkdomain 496 self.watchdog_fake.clk_domain = clkdomain 497 self.gpio0_fake.clk_domain = clkdomain 498 self.gpio1_fake.clk_domain = clkdomain 499 self.gpio2_fake.clk_domain = clkdomain 500 self.ssp_fake.clk_domain = clkdomain 501 self.sci_fake.clk_domain = clkdomain 502 self.aaci_fake.clk_domain = clkdomain 503 self.mmc_fake.clk_domain = clkdomain 504 self.rtc.clk_domain = clkdomain 505 self.flash_fake.clk_domain = clkdomain 506 self.smcreg_fake.clk_domain = clkdomain 507 self.energy_ctrl.clk_domain = clkdomain 508 509class VExpress_EMM(RealView): 510 _mem_regions = [(Addr('2GB'), Addr('2GB'))] 511 pci_cfg_base = 0x30000000 512 uart = Pl011(pio_addr=0x1c090000, int_num=37) 513 realview_io = VExpressCoreTileCtrl( 514 proc_id0=0x14000000, proc_id1=0x14000000, 515 idreg=0x02250000, pio_addr=0x1C010000) 516 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 517 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 518 generic_timer = GenericTimer(int_phys=29, int_virt=27) 519 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 520 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 521 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 522 hdlcd = HDLcd(pxl_clk=realview_io.osc_pxl, 523 pio_addr=0x2b000000, int_num=117) 524 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 525 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 526 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 527 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 528 io_shift = 2, ctrl_offset = 2, Command = 0x1, 529 BAR0 = 0x1C1A0000, BAR0Size = '256B', 530 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 531 BAR0LegacyIO = True, BAR1LegacyIO = True) 532 533 pciconfig = PciConfigAll(size='256MB') 534 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 535 conf_table_reported = False) 536 rtc = PL031(pio_addr=0x1C170000, int_num=36) 537 538 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 539 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 540 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 541 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 542 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 543 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 544 aaci_fake = AmbaFake(pio_addr=0x1C040000) 545 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 546 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 547 mmc_fake = AmbaFake(pio_addr=0x1c050000) 548 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 549 550 # Attach any PCI devices that are supported 551 def attachPciDevices(self): 552 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 553 InterruptLine=1, InterruptPin=1) 554 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 555 InterruptLine=2, InterruptPin=2) 556 557 def enableMSIX(self): 558 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 559 self.gicv2m = Gicv2m() 560 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 561 562 def setupBootLoader(self, mem_bus, cur_sys, loc): 563 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 564 conf_table_reported = False) 565 self.nvmem.port = mem_bus.master 566 cur_sys.boot_loader = loc('boot_emm.arm') 567 cur_sys.atags_addr = 0x8000000 568 cur_sys.load_addr_mask = 0xfffffff 569 cur_sys.load_offset = 0x80000000 570 571 # Attach I/O devices that are on chip and also set the appropriate 572 # ranges for the bridge 573 def attachOnChipIO(self, bus, bridge=None): 574 self.gic.pio = bus.master 575 self.vgic.pio = bus.master 576 self.local_cpu_timer.pio = bus.master 577 if hasattr(self, "gicv2m"): 578 self.gicv2m.pio = bus.master 579 self.hdlcd.dma = bus.slave 580 if bridge: 581 # Bridge ranges based on excluding what is part of on-chip I/O 582 # (gic, a9scu) 583 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 584 AddrRange(0x2B000000, size='4MB'), 585 AddrRange(0x30000000, size='256MB'), 586 AddrRange(0x40000000, size='512MB'), 587 AddrRange(0x18000000, size='64MB'), 588 AddrRange(0x1C000000, size='64MB')] 589 590 591 # Set the clock domain for IO objects that are considered 592 # to be "close" to the cores. 593 def onChipIOClkDomain(self, clkdomain): 594 self.gic.clk_domain = clkdomain 595 if hasattr(self, "gicv2m"): 596 self.gicv2m.clk_domain = clkdomain 597 self.hdlcd.clk_domain = clkdomain 598 self.vgic.clk_domain = clkdomain 599 600 # Attach I/O devices to specified bus object. Done here 601 # as the specified bus to connect to may not always be fixed. 602 def attachIO(self, bus): 603 self.uart.pio = bus.master 604 self.realview_io.pio = bus.master 605 self.timer0.pio = bus.master 606 self.timer1.pio = bus.master 607 self.clcd.pio = bus.master 608 self.clcd.dma = bus.slave 609 self.hdlcd.pio = bus.master 610 self.kmi0.pio = bus.master 611 self.kmi1.pio = bus.master 612 self.cf_ctrl.pio = bus.master 613 self.cf_ctrl.dma = bus.slave 614 self.cf_ctrl.config = bus.master 615 self.rtc.pio = bus.master 616 bus.use_default_range = True 617 self.vram.port = bus.master 618 self.pciconfig.pio = bus.default 619 620 self.l2x0_fake.pio = bus.master 621 self.uart1_fake.pio = bus.master 622 self.uart2_fake.pio = bus.master 623 self.uart3_fake.pio = bus.master 624 self.sp810_fake.pio = bus.master 625 self.watchdog_fake.pio = bus.master 626 self.aaci_fake.pio = bus.master 627 self.lan_fake.pio = bus.master 628 self.usb_fake.pio = bus.master 629 self.mmc_fake.pio = bus.master 630 self.energy_ctrl.pio = bus.master 631 632 # Try to attach the I/O if it exists 633 try: 634 self.ide.pio = bus.master 635 self.ide.config = bus.master 636 self.ide.dma = bus.slave 637 self.ethernet.pio = bus.master 638 self.ethernet.config = bus.master 639 self.ethernet.dma = bus.slave 640 except: 641 pass 642 643 # Set the clock domain for IO objects that are considered 644 # to be "far" away from the cores. 645 def offChipIOClkDomain(self, clkdomain): 646 self.uart.clk_domain = clkdomain 647 self.realview_io.clk_domain = clkdomain 648 self.timer0.clk_domain = clkdomain 649 self.timer1.clk_domain = clkdomain 650 self.clcd.clk_domain = clkdomain 651 self.kmi0.clk_domain = clkdomain 652 self.kmi1.clk_domain = clkdomain 653 self.cf_ctrl.clk_domain = clkdomain 654 self.rtc.clk_domain = clkdomain 655 self.vram.clk_domain = clkdomain 656 self.pciconfig.clk_domain = clkdomain 657 658 self.l2x0_fake.clk_domain = clkdomain 659 self.uart1_fake.clk_domain = clkdomain 660 self.uart2_fake.clk_domain = clkdomain 661 self.uart3_fake.clk_domain = clkdomain 662 self.sp810_fake.clk_domain = clkdomain 663 self.watchdog_fake.clk_domain = clkdomain 664 self.aaci_fake.clk_domain = clkdomain 665 self.lan_fake.clk_domain = clkdomain 666 self.usb_fake.clk_domain = clkdomain 667 self.mmc_fake.clk_domain = clkdomain 668 self.energy_ctrl.clk_domain = clkdomain 669 670class VExpress_EMM64(VExpress_EMM): 671 pci_io_base = 0x2f000000 672 pci_cfg_gen_offsets = True 673 # Three memory regions are specified totalling 512GB 674 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 675 (Addr('512GB'), Addr('480GB'))] 676 def setupBootLoader(self, mem_bus, cur_sys, loc): 677 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 678 self.nvmem.port = mem_bus.master 679 cur_sys.boot_loader = loc('boot_emm.arm64') 680 cur_sys.atags_addr = 0x8000000 681 cur_sys.load_addr_mask = 0xfffffff 682 cur_sys.load_offset = 0x80000000 683 684 685