RealView.py revision 10037:5cac77888310
1# Copyright (c) 2009-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54 55class AmbaPioDevice(BasicPioDevice): 56 type = 'AmbaPioDevice' 57 abstract = True 58 cxx_header = "dev/arm/amba_device.hh" 59 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 60 61class AmbaIntDevice(AmbaPioDevice): 62 type = 'AmbaIntDevice' 63 abstract = True 64 cxx_header = "dev/arm/amba_device.hh" 65 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 66 int_num = Param.UInt32("Interrupt number that connects to GIC") 67 int_delay = Param.Latency("100ns", 68 "Time between action and interrupt generation by device") 69 70class AmbaDmaDevice(DmaDevice): 71 type = 'AmbaDmaDevice' 72 abstract = True 73 cxx_header = "dev/arm/amba_device.hh" 74 pio_addr = Param.Addr("Address for AMBA slave interface") 75 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 76 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 77 int_num = Param.UInt32("Interrupt number that connects to GIC") 78 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 79 80class A9SCU(BasicPioDevice): 81 type = 'A9SCU' 82 cxx_header = "dev/arm/a9scu.hh" 83 84class RealViewCtrl(BasicPioDevice): 85 type = 'RealViewCtrl' 86 cxx_header = "dev/arm/rv_ctrl.hh" 87 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 88 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 89 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 90 91class VGic(PioDevice): 92 type = 'VGic' 93 cxx_header = "dev/arm/vgic.hh" 94 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 95 platform = Param.Platform(Parent.any, "Platform this device is part of.") 96 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 97 hv_addr = Param.Addr(0, "Address for hv control") 98 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 99 # The number of list registers is not currently configurable at runtime. 100 ppint = Param.UInt32("HV maintenance interrupt number") 101 102class AmbaFake(AmbaPioDevice): 103 type = 'AmbaFake' 104 cxx_header = "dev/arm/amba_fake.hh" 105 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 106 amba_id = 0; 107 108class Pl011(Uart): 109 type = 'Pl011' 110 cxx_header = "dev/arm/pl011.hh" 111 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 112 int_num = Param.UInt32("Interrupt number that connects to GIC") 113 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 114 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 115 116class Sp804(AmbaPioDevice): 117 type = 'Sp804' 118 cxx_header = "dev/arm/timer_sp804.hh" 119 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 120 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 121 clock0 = Param.Clock('1MHz', "Clock speed of the input") 122 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 123 clock1 = Param.Clock('1MHz', "Clock speed of the input") 124 amba_id = 0x00141804 125 126class CpuLocalTimer(BasicPioDevice): 127 type = 'CpuLocalTimer' 128 cxx_header = "dev/arm/timer_cpulocal.hh" 129 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 130 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 131 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 132 133class GenericTimer(SimObject): 134 type = 'GenericTimer' 135 cxx_header = "dev/arm/generic_timer.hh" 136 system = Param.System(Parent.any, "system") 137 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 138 int_num = Param.UInt32("Interrupt number used per-cpu to GIC") 139 # @todo: for now only one timer per CPU is supported, which is the 140 # normal behaviour when Security and Virt. extensions are disabled. 141 142class PL031(AmbaIntDevice): 143 type = 'PL031' 144 cxx_header = "dev/arm/rtc_pl031.hh" 145 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 146 amba_id = 0x00341031 147 148class Pl050(AmbaIntDevice): 149 type = 'Pl050' 150 cxx_header = "dev/arm/kmi.hh" 151 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 152 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 153 int_delay = '1us' 154 amba_id = 0x00141050 155 156class Pl111(AmbaDmaDevice): 157 type = 'Pl111' 158 cxx_header = "dev/arm/pl111.hh" 159 pixel_clock = Param.Clock('24MHz', "Pixel clock") 160 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 161 amba_id = 0x00141111 162 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 163 164 165class HDLcd(AmbaDmaDevice): 166 type = 'HDLcd' 167 cxx_header = "dev/arm/hdlcd.hh" 168 pixel_clock = Param.Clock('65MHz', "Clock frequency of the pixel clock " 169 "(i.e. PXLREFCLK / OSCCLK 5; 23.75MHz " 170 "default up to 165MHz)") 171 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 172 "display") 173 amba_id = 0x00141000 174 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 175 176class RealView(Platform): 177 type = 'RealView' 178 cxx_header = "dev/arm/realview.hh" 179 system = Param.System(Parent.any, "system") 180 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 181 mem_start_addr = Param.Addr(0, "Start address of main memory") 182 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 183 184 def setupBootLoader(self, mem_bus, cur_sys, loc): 185 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 186 conf_table_reported = False) 187 self.nvmem.port = mem_bus.master 188 cur_sys.boot_loader = loc('boot.arm') 189 cur_sys.atags_addr = 0x100 190 cur_sys.load_addr_mask = 0xfffffff 191 cur_sys.load_offset = 0 192 193 194# Reference for memory map and interrupt number 195# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 196# Chapter 4: Programmer's Reference 197class RealViewPBX(RealView): 198 uart = Pl011(pio_addr=0x10009000, int_num=44) 199 realview_io = RealViewCtrl(pio_addr=0x10000000) 200 gic = Pl390() 201 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 202 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 203 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 204 clcd = Pl111(pio_addr=0x10020000, int_num=55) 205 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 206 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 207 a9scu = A9SCU(pio_addr=0x1f000000) 208 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 209 io_shift = 1, ctrl_offset = 2, Command = 0x1, 210 BAR0 = 0x18000000, BAR0Size = '16B', 211 BAR1 = 0x18000100, BAR1Size = '1B', 212 BAR0LegacyIO = True, BAR1LegacyIO = True) 213 214 215 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 216 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 217 fake_mem=True) 218 dmac_fake = AmbaFake(pio_addr=0x10030000) 219 uart1_fake = AmbaFake(pio_addr=0x1000a000) 220 uart2_fake = AmbaFake(pio_addr=0x1000b000) 221 uart3_fake = AmbaFake(pio_addr=0x1000c000) 222 smc_fake = AmbaFake(pio_addr=0x100e1000) 223 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 224 watchdog_fake = AmbaFake(pio_addr=0x10010000) 225 gpio0_fake = AmbaFake(pio_addr=0x10013000) 226 gpio1_fake = AmbaFake(pio_addr=0x10014000) 227 gpio2_fake = AmbaFake(pio_addr=0x10015000) 228 ssp_fake = AmbaFake(pio_addr=0x1000d000) 229 sci_fake = AmbaFake(pio_addr=0x1000e000) 230 aaci_fake = AmbaFake(pio_addr=0x10004000) 231 mmc_fake = AmbaFake(pio_addr=0x10005000) 232 rtc = PL031(pio_addr=0x10017000, int_num=42) 233 234 235 # Attach I/O devices that are on chip and also set the appropriate 236 # ranges for the bridge 237 def attachOnChipIO(self, bus, bridge): 238 self.gic.pio = bus.master 239 self.l2x0_fake.pio = bus.master 240 self.a9scu.pio = bus.master 241 self.local_cpu_timer.pio = bus.master 242 # Bridge ranges based on excluding what is part of on-chip I/O 243 # (gic, l2x0, a9scu, local_cpu_timer) 244 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 245 self.a9scu.pio_addr - 1), 246 AddrRange(self.flash_fake.pio_addr, 247 self.flash_fake.pio_addr + \ 248 self.flash_fake.pio_size - 1)] 249 250 # Attach I/O devices to specified bus object. Can't do this 251 # earlier, since the bus object itself is typically defined at the 252 # System level. 253 def attachIO(self, bus): 254 self.uart.pio = bus.master 255 self.realview_io.pio = bus.master 256 self.timer0.pio = bus.master 257 self.timer1.pio = bus.master 258 self.clcd.pio = bus.master 259 self.clcd.dma = bus.slave 260 self.kmi0.pio = bus.master 261 self.kmi1.pio = bus.master 262 self.cf_ctrl.pio = bus.master 263 self.cf_ctrl.config = bus.master 264 self.cf_ctrl.dma = bus.slave 265 self.dmac_fake.pio = bus.master 266 self.uart1_fake.pio = bus.master 267 self.uart2_fake.pio = bus.master 268 self.uart3_fake.pio = bus.master 269 self.smc_fake.pio = bus.master 270 self.sp810_fake.pio = bus.master 271 self.watchdog_fake.pio = bus.master 272 self.gpio0_fake.pio = bus.master 273 self.gpio1_fake.pio = bus.master 274 self.gpio2_fake.pio = bus.master 275 self.ssp_fake.pio = bus.master 276 self.sci_fake.pio = bus.master 277 self.aaci_fake.pio = bus.master 278 self.mmc_fake.pio = bus.master 279 self.rtc.pio = bus.master 280 self.flash_fake.pio = bus.master 281 282# Reference for memory map and interrupt number 283# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 284# Chapter 4: Programmer's Reference 285class RealViewEB(RealView): 286 uart = Pl011(pio_addr=0x10009000, int_num=44) 287 realview_io = RealViewCtrl(pio_addr=0x10000000) 288 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 289 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 290 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 291 clcd = Pl111(pio_addr=0x10020000, int_num=23) 292 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 293 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 294 295 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 296 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 297 fake_mem=True) 298 dmac_fake = AmbaFake(pio_addr=0x10030000) 299 uart1_fake = AmbaFake(pio_addr=0x1000a000) 300 uart2_fake = AmbaFake(pio_addr=0x1000b000) 301 uart3_fake = AmbaFake(pio_addr=0x1000c000) 302 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 303 smc_fake = AmbaFake(pio_addr=0x100e1000) 304 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 305 watchdog_fake = AmbaFake(pio_addr=0x10010000) 306 gpio0_fake = AmbaFake(pio_addr=0x10013000) 307 gpio1_fake = AmbaFake(pio_addr=0x10014000) 308 gpio2_fake = AmbaFake(pio_addr=0x10015000) 309 ssp_fake = AmbaFake(pio_addr=0x1000d000) 310 sci_fake = AmbaFake(pio_addr=0x1000e000) 311 aaci_fake = AmbaFake(pio_addr=0x10004000) 312 mmc_fake = AmbaFake(pio_addr=0x10005000) 313 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 314 315 316 317 # Attach I/O devices that are on chip and also set the appropriate 318 # ranges for the bridge 319 def attachOnChipIO(self, bus, bridge): 320 self.gic.pio = bus.master 321 self.l2x0_fake.pio = bus.master 322 # Bridge ranges based on excluding what is part of on-chip I/O 323 # (gic, l2x0) 324 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 325 self.gic.cpu_addr - 1), 326 AddrRange(self.flash_fake.pio_addr, Addr.max)] 327 328 # Attach I/O devices to specified bus object. Can't do this 329 # earlier, since the bus object itself is typically defined at the 330 # System level. 331 def attachIO(self, bus): 332 self.uart.pio = bus.master 333 self.realview_io.pio = bus.master 334 self.timer0.pio = bus.master 335 self.timer1.pio = bus.master 336 self.clcd.pio = bus.master 337 self.clcd.dma = bus.slave 338 self.kmi0.pio = bus.master 339 self.kmi1.pio = bus.master 340 self.dmac_fake.pio = bus.master 341 self.uart1_fake.pio = bus.master 342 self.uart2_fake.pio = bus.master 343 self.uart3_fake.pio = bus.master 344 self.smc_fake.pio = bus.master 345 self.sp810_fake.pio = bus.master 346 self.watchdog_fake.pio = bus.master 347 self.gpio0_fake.pio = bus.master 348 self.gpio1_fake.pio = bus.master 349 self.gpio2_fake.pio = bus.master 350 self.ssp_fake.pio = bus.master 351 self.sci_fake.pio = bus.master 352 self.aaci_fake.pio = bus.master 353 self.mmc_fake.pio = bus.master 354 self.rtc_fake.pio = bus.master 355 self.flash_fake.pio = bus.master 356 self.smcreg_fake.pio = bus.master 357 358class VExpress_EMM(RealView): 359 mem_start_addr = '2GB' 360 max_mem_size = '2GB' 361 pci_cfg_base = 0x30000000 362 uart = Pl011(pio_addr=0x1c090000, int_num=37) 363 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 364 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 365 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 366 generic_timer = GenericTimer(int_num=29) 367 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 368 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 369 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 370 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 371 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 372 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 373 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 374 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 375 io_shift = 2, ctrl_offset = 2, Command = 0x1, 376 BAR0 = 0x1C1A0000, BAR0Size = '256B', 377 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 378 BAR0LegacyIO = True, BAR1LegacyIO = True) 379 380 pciconfig = PciConfigAll(size='256MB') 381 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 382 InterruptLine=1, InterruptPin=1) 383 384 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 385 InterruptLine=2, InterruptPin=2) 386 387 388 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 389 conf_table_reported = False) 390 rtc = PL031(pio_addr=0x1C170000, int_num=36) 391 392 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 393 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 394 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 395 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 396 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 397 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 398 aaci_fake = AmbaFake(pio_addr=0x1C040000) 399 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 400 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 401 mmc_fake = AmbaFake(pio_addr=0x1c050000) 402 403 def setupBootLoader(self, mem_bus, cur_sys, loc): 404 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 405 conf_table_reported = False) 406 self.nvmem.port = mem_bus.master 407 cur_sys.boot_loader = loc('boot_emm.arm') 408 cur_sys.atags_addr = 0x8000000 409 cur_sys.load_addr_mask = 0xfffffff 410 cur_sys.load_offset = 0x80000000 411 412 # Attach I/O devices that are on chip and also set the appropriate 413 # ranges for the bridge 414 def attachOnChipIO(self, bus, bridge): 415 self.gic.pio = bus.master 416 self.local_cpu_timer.pio = bus.master 417 self.hdlcd.dma = bus.slave 418 # Bridge ranges based on excluding what is part of on-chip I/O 419 # (gic, a9scu) 420 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 421 AddrRange(0x2B000000, size='4MB'), 422 AddrRange(0x30000000, size='256MB'), 423 AddrRange(0x40000000, size='512MB'), 424 AddrRange(0x18000000, size='64MB'), 425 AddrRange(0x1C000000, size='64MB')] 426 self.vgic.pio = bus.master 427 428 429 # Attach I/O devices to specified bus object. Can't do this 430 # earlier, since the bus object itself is typically defined at the 431 # System level. 432 def attachIO(self, bus): 433 self.uart.pio = bus.master 434 self.realview_io.pio = bus.master 435 self.timer0.pio = bus.master 436 self.timer1.pio = bus.master 437 self.clcd.pio = bus.master 438 self.clcd.dma = bus.slave 439 self.hdlcd.pio = bus.master 440 self.kmi0.pio = bus.master 441 self.kmi1.pio = bus.master 442 self.cf_ctrl.pio = bus.master 443 self.cf_ctrl.dma = bus.slave 444 self.cf_ctrl.config = bus.master 445 self.rtc.pio = bus.master 446 bus.use_default_range = True 447 self.vram.port = bus.master 448 self.ide.pio = bus.master 449 self.ide.config = bus.master 450 self.ide.dma = bus.slave 451 self.ethernet.pio = bus.master 452 self.ethernet.config = bus.master 453 self.ethernet.dma = bus.slave 454 self.pciconfig.pio = bus.default 455 456 self.l2x0_fake.pio = bus.master 457 self.uart1_fake.pio = bus.master 458 self.uart2_fake.pio = bus.master 459 self.uart3_fake.pio = bus.master 460 self.sp810_fake.pio = bus.master 461 self.watchdog_fake.pio = bus.master 462 self.aaci_fake.pio = bus.master 463 self.lan_fake.pio = bus.master 464 self.usb_fake.pio = bus.master 465 self.mmc_fake.pio = bus.master 466 467class VExpress_EMM64(VExpress_EMM): 468 def setupBootLoader(self, mem_bus, cur_sys, loc): 469 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 470 self.nvmem.port = mem_bus.master 471 cur_sys.boot_loader = loc('boot_emm.arm64') 472 cur_sys.atags_addr = 0x8000000 473 cur_sys.load_addr_mask = 0xfffffff 474 cur_sys.load_offset = 0x80000000 475 476 477