RealView.py revision 8847:ef8630054b5e
1# Copyright (c) 2009-2011 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52 53class AmbaDevice(BasicPioDevice): 54 type = 'AmbaDevice' 55 abstract = True 56 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 57 58class AmbaIntDevice(AmbaDevice): 59 type = 'AmbaIntDevice' 60 abstract = True 61 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 62 int_num = Param.UInt32("Interrupt number that connects to GIC") 63 int_delay = Param.Latency("100ns", 64 "Time between action and interrupt generation by device") 65 66class AmbaDmaDevice(DmaDevice): 67 type = 'AmbaDmaDevice' 68 abstract = True 69 pio_addr = Param.Addr("Address for AMBA slave interface") 70 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 71 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 72 int_num = Param.UInt32("Interrupt number that connects to GIC") 73 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 74 75class A9SCU(BasicPioDevice): 76 type = 'A9SCU' 77 78class RealViewCtrl(BasicPioDevice): 79 type = 'RealViewCtrl' 80 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 81 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 82 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 83 84class Gic(PioDevice): 85 type = 'Gic' 86 platform = Param.Platform(Parent.any, "Platform this device is part of.") 87 dist_addr = Param.Addr(0x1f001000, "Address for distributor") 88 cpu_addr = Param.Addr(0x1f000100, "Address for cpu") 89 dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor") 90 cpu_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to cpu interface") 91 int_latency = Param.Latency('10ns', "Delay for interrupt to get to CPU") 92 it_lines = Param.UInt32(128, "Number of interrupt lines supported (max = 1020)") 93 94class AmbaFake(AmbaDevice): 95 type = 'AmbaFake' 96 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 97 amba_id = 0; 98 99class Pl011(Uart): 100 type = 'Pl011' 101 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 102 int_num = Param.UInt32("Interrupt number that connects to GIC") 103 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 104 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 105 106class Sp804(AmbaDevice): 107 type = 'Sp804' 108 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 109 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 110 clock0 = Param.Clock('1MHz', "Clock speed of the input") 111 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 112 clock1 = Param.Clock('1MHz', "Clock speed of the input") 113 amba_id = 0x00141804 114 115class CpuLocalTimer(BasicPioDevice): 116 type = 'CpuLocalTimer' 117 gic = Param.Gic(Parent.any, "Gic to use for interrupting") 118 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 119 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 120 clock = Param.Clock('1GHz', "Clock speed at which the timer counts") 121 122class Pl050(AmbaIntDevice): 123 type = 'Pl050' 124 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 125 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 126 int_delay = '1us' 127 amba_id = 0x00141050 128 129class Pl111(AmbaDmaDevice): 130 type = 'Pl111' 131 clock = Param.Clock('24MHz', "Clock speed of the input") 132 vnc = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display") 133 amba_id = 0x00141111 134 135class RealView(Platform): 136 type = 'RealView' 137 system = Param.System(Parent.any, "system") 138 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 139 140# Reference for memory map and interrupt number 141# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 142# Chapter 4: Programmer's Reference 143class RealViewPBX(RealView): 144 uart = Pl011(pio_addr=0x10009000, int_num=44) 145 realview_io = RealViewCtrl(pio_addr=0x10000000) 146 gic = Gic() 147 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 148 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 149 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 150 clcd = Pl111(pio_addr=0x10020000, int_num=55) 151 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 152 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 153 a9scu = A9SCU(pio_addr=0x1f000000) 154 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 155 io_shift = 1, ctrl_offset = 2, Command = 0x1, 156 BAR0 = 0x18000000, BAR0Size = '16B', 157 BAR1 = 0x18000100, BAR1Size = '1B', 158 BAR0LegacyIO = True, BAR1LegacyIO = True) 159 160 161 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 162 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 163 fake_mem=True) 164 dmac_fake = AmbaFake(pio_addr=0x10030000) 165 uart1_fake = AmbaFake(pio_addr=0x1000a000) 166 uart2_fake = AmbaFake(pio_addr=0x1000b000) 167 uart3_fake = AmbaFake(pio_addr=0x1000c000) 168 smc_fake = AmbaFake(pio_addr=0x100e1000) 169 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 170 watchdog_fake = AmbaFake(pio_addr=0x10010000) 171 gpio0_fake = AmbaFake(pio_addr=0x10013000) 172 gpio1_fake = AmbaFake(pio_addr=0x10014000) 173 gpio2_fake = AmbaFake(pio_addr=0x10015000) 174 ssp_fake = AmbaFake(pio_addr=0x1000d000) 175 sci_fake = AmbaFake(pio_addr=0x1000e000) 176 aaci_fake = AmbaFake(pio_addr=0x10004000) 177 mmc_fake = AmbaFake(pio_addr=0x10005000) 178 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 179 180 181 # Attach I/O devices that are on chip and also set the appropriate 182 # ranges for the bridge 183 def attachOnChipIO(self, bus, bridge): 184 self.gic.pio = bus.master 185 self.l2x0_fake.pio = bus.master 186 self.a9scu.pio = bus.master 187 self.local_cpu_timer.pio = bus.master 188 # Bridge ranges based on excluding what is part of on-chip I/O 189 # (gic, l2x0, a9scu, local_cpu_timer) 190 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 191 self.a9scu.pio_addr - 1), 192 AddrRange(self.flash_fake.pio_addr, Addr.max)] 193 194 # Attach I/O devices to specified bus object. Can't do this 195 # earlier, since the bus object itself is typically defined at the 196 # System level. 197 def attachIO(self, bus): 198 self.uart.pio = bus.master 199 self.realview_io.pio = bus.master 200 self.timer0.pio = bus.master 201 self.timer1.pio = bus.master 202 self.clcd.pio = bus.master 203 self.clcd.dma = bus.slave 204 self.kmi0.pio = bus.master 205 self.kmi1.pio = bus.master 206 self.cf_ctrl.pio = bus.master 207 self.cf_ctrl.config = bus.master 208 self.cf_ctrl.dma = bus.slave 209 self.dmac_fake.pio = bus.master 210 self.uart1_fake.pio = bus.master 211 self.uart2_fake.pio = bus.master 212 self.uart3_fake.pio = bus.master 213 self.smc_fake.pio = bus.master 214 self.sp810_fake.pio = bus.master 215 self.watchdog_fake.pio = bus.master 216 self.gpio0_fake.pio = bus.master 217 self.gpio1_fake.pio = bus.master 218 self.gpio2_fake.pio = bus.master 219 self.ssp_fake.pio = bus.master 220 self.sci_fake.pio = bus.master 221 self.aaci_fake.pio = bus.master 222 self.mmc_fake.pio = bus.master 223 self.rtc_fake.pio = bus.master 224 self.flash_fake.pio = bus.master 225 226# Reference for memory map and interrupt number 227# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 228# Chapter 4: Programmer's Reference 229class RealViewEB(RealView): 230 uart = Pl011(pio_addr=0x10009000, int_num=44) 231 realview_io = RealViewCtrl(pio_addr=0x10000000) 232 gic = Gic(dist_addr=0x10041000, cpu_addr=0x10040000) 233 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 234 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 235 clcd = Pl111(pio_addr=0x10020000, int_num=23) 236 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 237 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 238 239 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 240 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 241 fake_mem=True) 242 dmac_fake = AmbaFake(pio_addr=0x10030000) 243 uart1_fake = AmbaFake(pio_addr=0x1000a000) 244 uart2_fake = AmbaFake(pio_addr=0x1000b000) 245 uart3_fake = AmbaFake(pio_addr=0x1000c000) 246 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 247 smc_fake = AmbaFake(pio_addr=0x100e1000) 248 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 249 watchdog_fake = AmbaFake(pio_addr=0x10010000) 250 gpio0_fake = AmbaFake(pio_addr=0x10013000) 251 gpio1_fake = AmbaFake(pio_addr=0x10014000) 252 gpio2_fake = AmbaFake(pio_addr=0x10015000) 253 ssp_fake = AmbaFake(pio_addr=0x1000d000) 254 sci_fake = AmbaFake(pio_addr=0x1000e000) 255 aaci_fake = AmbaFake(pio_addr=0x10004000) 256 mmc_fake = AmbaFake(pio_addr=0x10005000) 257 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 258 259 260 261 # Attach I/O devices that are on chip and also set the appropriate 262 # ranges for the bridge 263 def attachOnChipIO(self, bus, bridge): 264 self.gic.pio = bus.master 265 self.l2x0_fake.pio = bus.master 266 # Bridge ranges based on excluding what is part of on-chip I/O 267 # (gic, l2x0) 268 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 269 self.gic.cpu_addr - 1), 270 AddrRange(self.flash_fake.pio_addr, Addr.max)] 271 272 # Attach I/O devices to specified bus object. Can't do this 273 # earlier, since the bus object itself is typically defined at the 274 # System level. 275 def attachIO(self, bus): 276 self.uart.pio = bus.master 277 self.realview_io.pio = bus.master 278 self.timer0.pio = bus.master 279 self.timer1.pio = bus.master 280 self.clcd.pio = bus.master 281 self.clcd.dma = bus.slave 282 self.kmi0.pio = bus.master 283 self.kmi1.pio = bus.master 284 self.dmac_fake.pio = bus.master 285 self.uart1_fake.pio = bus.master 286 self.uart2_fake.pio = bus.master 287 self.uart3_fake.pio = bus.master 288 self.smc_fake.pio = bus.master 289 self.sp810_fake.pio = bus.master 290 self.watchdog_fake.pio = bus.master 291 self.gpio0_fake.pio = bus.master 292 self.gpio1_fake.pio = bus.master 293 self.gpio2_fake.pio = bus.master 294 self.ssp_fake.pio = bus.master 295 self.sci_fake.pio = bus.master 296 self.aaci_fake.pio = bus.master 297 self.mmc_fake.pio = bus.master 298 self.rtc_fake.pio = bus.master 299 self.flash_fake.pio = bus.master 300 self.smcreg_fake.pio = bus.master 301 302class VExpress_ELT(RealView): 303 pci_cfg_base = 0xD0000000 304 elba_uart = Pl011(pio_addr=0xE0009000, int_num=42) 305 uart = Pl011(pio_addr=0xFF009000, int_num=121) 306 realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000) 307 gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100) 308 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600) 309 v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000) 310 v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000) 311 elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz') 312 elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz') 313 clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown 314 kmi0 = Pl050(pio_addr=0xFF006000, int_num=124) 315 kmi1 = Pl050(pio_addr=0xFF007000, int_num=125) 316 elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52) 317 elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53) 318 a9scu = A9SCU(pio_addr=0xE0200000) 319 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 320 io_shift = 2, ctrl_offset = 2, Command = 0x1, 321 BAR0 = 0xFF01A000, BAR0Size = '256B', 322 BAR1 = 0xFF01A100, BAR1Size = '4096B', 323 BAR0LegacyIO = True, BAR1LegacyIO = True) 324 325 pciconfig = PciConfigAll() 326 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 327 InterruptLine=1, InterruptPin=1) 328 329 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 330 InterruptLine=2, InterruptPin=2) 331 332 l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff) 333 dmac_fake = AmbaFake(pio_addr=0xE0020000) 334 uart1_fake = AmbaFake(pio_addr=0xE000A000) 335 uart2_fake = AmbaFake(pio_addr=0xE000B000) 336 uart3_fake = AmbaFake(pio_addr=0xE000C000) 337 smc_fake = AmbaFake(pio_addr=0xEC000000) 338 sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True) 339 watchdog_fake = AmbaFake(pio_addr=0xE0010000) 340 aaci_fake = AmbaFake(pio_addr=0xFF004000) 341 elba_aaci_fake = AmbaFake(pio_addr=0xE0004000) 342 mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this 343 rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031) 344 spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000) 345 lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff) 346 usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff) 347 348 349 # Attach I/O devices that are on chip and also set the appropriate 350 # ranges for the bridge 351 def attachOnChipIO(self, bus, bridge): 352 self.gic.pio = bus.master 353 self.a9scu.pio = bus.master 354 self.local_cpu_timer.pio = bus.master 355 # Bridge ranges based on excluding what is part of on-chip I/O 356 # (gic, a9scu) 357 bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1), 358 AddrRange(self.l2x0_fake.pio_addr, Addr.max)] 359 360 # Attach I/O devices to specified bus object. Can't do this 361 # earlier, since the bus object itself is typically defined at the 362 # System level. 363 def attachIO(self, bus): 364 self.elba_uart.pio = bus.master 365 self.uart.pio = bus.master 366 self.realview_io.pio = bus.master 367 self.v2m_timer0.pio = bus.master 368 self.v2m_timer1.pio = bus.master 369 self.elba_timer0.pio = bus.master 370 self.elba_timer1.pio = bus.master 371 self.clcd.pio = bus.master 372 self.clcd.dma = bus.slave 373 self.kmi0.pio = bus.master 374 self.kmi1.pio = bus.master 375 self.elba_kmi0.pio = bus.master 376 self.elba_kmi1.pio = bus.master 377 self.cf_ctrl.pio = bus.master 378 self.cf_ctrl.config = bus.master 379 self.cf_ctrl.dma = bus.slave 380 self.ide.pio = bus.master 381 self.ide.config = bus.master 382 self.ide.dma = bus.slave 383 self.ethernet.pio = bus.master 384 self.ethernet.config = bus.master 385 self.ethernet.dma = bus.slave 386 self.pciconfig.pio = bus.default 387 bus.use_default_range = True 388 389 self.l2x0_fake.pio = bus.master 390 self.dmac_fake.pio = bus.master 391 self.uart1_fake.pio = bus.master 392 self.uart2_fake.pio = bus.master 393 self.uart3_fake.pio = bus.master 394 self.smc_fake.pio = bus.master 395 self.sp810_fake.pio = bus.master 396 self.watchdog_fake.pio = bus.master 397 self.aaci_fake.pio = bus.master 398 self.elba_aaci_fake.pio = bus.master 399 self.mmc_fake.pio = bus.master 400 self.rtc_fake.pio = bus.master 401 self.spsc_fake.pio = bus.master 402 self.lan_fake.pio = bus.master 403 self.usb_fake.pio = bus.master 404 405