RealView.py revision 9788:5558ee8dd7d9
1# Copyright (c) 2009-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_e1000, IGbE_igb 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54 55class AmbaDevice(BasicPioDevice): 56 type = 'AmbaDevice' 57 abstract = True 58 cxx_header = "dev/arm/amba_device.hh" 59 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 60 61class AmbaIntDevice(AmbaDevice): 62 type = 'AmbaIntDevice' 63 abstract = True 64 cxx_header = "dev/arm/amba_device.hh" 65 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 66 int_num = Param.UInt32("Interrupt number that connects to GIC") 67 int_delay = Param.Latency("100ns", 68 "Time between action and interrupt generation by device") 69 70class AmbaDmaDevice(DmaDevice): 71 type = 'AmbaDmaDevice' 72 abstract = True 73 cxx_header = "dev/arm/amba_device.hh" 74 pio_addr = Param.Addr("Address for AMBA slave interface") 75 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 76 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 77 int_num = Param.UInt32("Interrupt number that connects to GIC") 78 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 79 80class A9SCU(BasicPioDevice): 81 type = 'A9SCU' 82 cxx_header = "dev/arm/a9scu.hh" 83 84class RealViewCtrl(BasicPioDevice): 85 type = 'RealViewCtrl' 86 cxx_header = "dev/arm/rv_ctrl.hh" 87 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 88 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 89 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 90 91class AmbaFake(AmbaDevice): 92 type = 'AmbaFake' 93 cxx_header = "dev/arm/amba_fake.hh" 94 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 95 amba_id = 0; 96 97class Pl011(Uart): 98 type = 'Pl011' 99 cxx_header = "dev/arm/pl011.hh" 100 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 101 int_num = Param.UInt32("Interrupt number that connects to GIC") 102 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 103 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 104 105class Sp804(AmbaDevice): 106 type = 'Sp804' 107 cxx_header = "dev/arm/timer_sp804.hh" 108 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 109 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 110 clock0 = Param.Clock('1MHz', "Clock speed of the input") 111 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 112 clock1 = Param.Clock('1MHz', "Clock speed of the input") 113 amba_id = 0x00141804 114 115class CpuLocalTimer(BasicPioDevice): 116 type = 'CpuLocalTimer' 117 cxx_header = "dev/arm/timer_cpulocal.hh" 118 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 119 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 120 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 121 122class PL031(AmbaIntDevice): 123 type = 'PL031' 124 cxx_header = "dev/arm/rtc_pl031.hh" 125 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 126 amba_id = 0x00341031 127 128class Pl050(AmbaIntDevice): 129 type = 'Pl050' 130 cxx_header = "dev/arm/kmi.hh" 131 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 132 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 133 int_delay = '1us' 134 amba_id = 0x00141050 135 136class Pl111(AmbaDmaDevice): 137 type = 'Pl111' 138 cxx_header = "dev/arm/pl111.hh" 139 pixel_clock = Param.Clock('24MHz', "Pixel clock") 140 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 141 amba_id = 0x00141111 142 143class HDLcd(AmbaDmaDevice): 144 type = 'HDLcd' 145 cxx_header = "dev/arm/hdlcd.hh" 146 pixel_clock = Param.Clock('65MHz', "Clock frequency of the pixel clock " 147 "(i.e. PXLREFCLK / OSCCLK 5; 23.75MHz " 148 "default up to 165MHz)") 149 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 150 "display") 151 amba_id = 0x00141000 152 153class RealView(Platform): 154 type = 'RealView' 155 cxx_header = "dev/arm/realview.hh" 156 system = Param.System(Parent.any, "system") 157 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 158 mem_start_addr = Param.Addr(0, "Start address of main memory") 159 max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") 160 161 def setupBootLoader(self, mem_bus, cur_sys, loc): 162 self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), 163 size = '64MB')) 164 self.nvmem.port = mem_bus.master 165 cur_sys.boot_loader = loc('boot.arm') 166 167 168# Reference for memory map and interrupt number 169# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 170# Chapter 4: Programmer's Reference 171class RealViewPBX(RealView): 172 uart = Pl011(pio_addr=0x10009000, int_num=44) 173 realview_io = RealViewCtrl(pio_addr=0x10000000) 174 gic = Pl390() 175 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 176 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 177 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 178 clcd = Pl111(pio_addr=0x10020000, int_num=55) 179 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 180 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 181 a9scu = A9SCU(pio_addr=0x1f000000) 182 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 183 io_shift = 1, ctrl_offset = 2, Command = 0x1, 184 BAR0 = 0x18000000, BAR0Size = '16B', 185 BAR1 = 0x18000100, BAR1Size = '1B', 186 BAR0LegacyIO = True, BAR1LegacyIO = True) 187 188 189 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 190 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 191 fake_mem=True) 192 dmac_fake = AmbaFake(pio_addr=0x10030000) 193 uart1_fake = AmbaFake(pio_addr=0x1000a000) 194 uart2_fake = AmbaFake(pio_addr=0x1000b000) 195 uart3_fake = AmbaFake(pio_addr=0x1000c000) 196 smc_fake = AmbaFake(pio_addr=0x100e1000) 197 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 198 watchdog_fake = AmbaFake(pio_addr=0x10010000) 199 gpio0_fake = AmbaFake(pio_addr=0x10013000) 200 gpio1_fake = AmbaFake(pio_addr=0x10014000) 201 gpio2_fake = AmbaFake(pio_addr=0x10015000) 202 ssp_fake = AmbaFake(pio_addr=0x1000d000) 203 sci_fake = AmbaFake(pio_addr=0x1000e000) 204 aaci_fake = AmbaFake(pio_addr=0x10004000) 205 mmc_fake = AmbaFake(pio_addr=0x10005000) 206 rtc = PL031(pio_addr=0x10017000, int_num=42) 207 208 209 # Attach I/O devices that are on chip and also set the appropriate 210 # ranges for the bridge 211 def attachOnChipIO(self, bus, bridge): 212 self.gic.pio = bus.master 213 self.l2x0_fake.pio = bus.master 214 self.a9scu.pio = bus.master 215 self.local_cpu_timer.pio = bus.master 216 # Bridge ranges based on excluding what is part of on-chip I/O 217 # (gic, l2x0, a9scu, local_cpu_timer) 218 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 219 self.a9scu.pio_addr - 1), 220 AddrRange(self.flash_fake.pio_addr, 221 self.flash_fake.pio_addr + \ 222 self.flash_fake.pio_size - 1)] 223 224 # Attach I/O devices to specified bus object. Can't do this 225 # earlier, since the bus object itself is typically defined at the 226 # System level. 227 def attachIO(self, bus): 228 self.uart.pio = bus.master 229 self.realview_io.pio = bus.master 230 self.timer0.pio = bus.master 231 self.timer1.pio = bus.master 232 self.clcd.pio = bus.master 233 self.clcd.dma = bus.slave 234 self.kmi0.pio = bus.master 235 self.kmi1.pio = bus.master 236 self.cf_ctrl.pio = bus.master 237 self.cf_ctrl.config = bus.master 238 self.cf_ctrl.dma = bus.slave 239 self.dmac_fake.pio = bus.master 240 self.uart1_fake.pio = bus.master 241 self.uart2_fake.pio = bus.master 242 self.uart3_fake.pio = bus.master 243 self.smc_fake.pio = bus.master 244 self.sp810_fake.pio = bus.master 245 self.watchdog_fake.pio = bus.master 246 self.gpio0_fake.pio = bus.master 247 self.gpio1_fake.pio = bus.master 248 self.gpio2_fake.pio = bus.master 249 self.ssp_fake.pio = bus.master 250 self.sci_fake.pio = bus.master 251 self.aaci_fake.pio = bus.master 252 self.mmc_fake.pio = bus.master 253 self.rtc.pio = bus.master 254 self.flash_fake.pio = bus.master 255 256# Reference for memory map and interrupt number 257# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 258# Chapter 4: Programmer's Reference 259class RealViewEB(RealView): 260 uart = Pl011(pio_addr=0x10009000, int_num=44) 261 realview_io = RealViewCtrl(pio_addr=0x10000000) 262 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 263 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 264 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 265 clcd = Pl111(pio_addr=0x10020000, int_num=23) 266 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 267 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 268 269 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 270 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 271 fake_mem=True) 272 dmac_fake = AmbaFake(pio_addr=0x10030000) 273 uart1_fake = AmbaFake(pio_addr=0x1000a000) 274 uart2_fake = AmbaFake(pio_addr=0x1000b000) 275 uart3_fake = AmbaFake(pio_addr=0x1000c000) 276 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 277 smc_fake = AmbaFake(pio_addr=0x100e1000) 278 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 279 watchdog_fake = AmbaFake(pio_addr=0x10010000) 280 gpio0_fake = AmbaFake(pio_addr=0x10013000) 281 gpio1_fake = AmbaFake(pio_addr=0x10014000) 282 gpio2_fake = AmbaFake(pio_addr=0x10015000) 283 ssp_fake = AmbaFake(pio_addr=0x1000d000) 284 sci_fake = AmbaFake(pio_addr=0x1000e000) 285 aaci_fake = AmbaFake(pio_addr=0x10004000) 286 mmc_fake = AmbaFake(pio_addr=0x10005000) 287 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 288 289 290 291 # Attach I/O devices that are on chip and also set the appropriate 292 # ranges for the bridge 293 def attachOnChipIO(self, bus, bridge): 294 self.gic.pio = bus.master 295 self.l2x0_fake.pio = bus.master 296 # Bridge ranges based on excluding what is part of on-chip I/O 297 # (gic, l2x0) 298 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 299 self.gic.cpu_addr - 1), 300 AddrRange(self.flash_fake.pio_addr, Addr.max)] 301 302 # Attach I/O devices to specified bus object. Can't do this 303 # earlier, since the bus object itself is typically defined at the 304 # System level. 305 def attachIO(self, bus): 306 self.uart.pio = bus.master 307 self.realview_io.pio = bus.master 308 self.timer0.pio = bus.master 309 self.timer1.pio = bus.master 310 self.clcd.pio = bus.master 311 self.clcd.dma = bus.slave 312 self.kmi0.pio = bus.master 313 self.kmi1.pio = bus.master 314 self.dmac_fake.pio = bus.master 315 self.uart1_fake.pio = bus.master 316 self.uart2_fake.pio = bus.master 317 self.uart3_fake.pio = bus.master 318 self.smc_fake.pio = bus.master 319 self.sp810_fake.pio = bus.master 320 self.watchdog_fake.pio = bus.master 321 self.gpio0_fake.pio = bus.master 322 self.gpio1_fake.pio = bus.master 323 self.gpio2_fake.pio = bus.master 324 self.ssp_fake.pio = bus.master 325 self.sci_fake.pio = bus.master 326 self.aaci_fake.pio = bus.master 327 self.mmc_fake.pio = bus.master 328 self.rtc_fake.pio = bus.master 329 self.flash_fake.pio = bus.master 330 self.smcreg_fake.pio = bus.master 331 332class VExpress_EMM(RealView): 333 mem_start_addr = '2GB' 334 max_mem_size = '2GB' 335 pci_cfg_base = 0x30000000 336 uart = Pl011(pio_addr=0x1c090000, int_num=37) 337 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000) 338 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 339 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 340 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 341 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 342 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 343 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 344 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 345 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 346 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 347 io_shift = 2, ctrl_offset = 2, Command = 0x1, 348 BAR0 = 0x1C1A0000, BAR0Size = '256B', 349 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 350 BAR0LegacyIO = True, BAR1LegacyIO = True) 351 352 pciconfig = PciConfigAll(size='256MB') 353 ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 354 InterruptLine=1, InterruptPin=1) 355 356 ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 357 InterruptLine=2, InterruptPin=2) 358 359 360 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB')) 361 rtc = PL031(pio_addr=0x1C170000, int_num=36) 362 363 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 364 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 365 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 366 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 367 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 368 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 369 aaci_fake = AmbaFake(pio_addr=0x1C040000) 370 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 371 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 372 mmc_fake = AmbaFake(pio_addr=0x1c050000) 373 374 def setupBootLoader(self, mem_bus, cur_sys, loc): 375 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 376 self.nvmem.port = mem_bus.master 377 cur_sys.boot_loader = loc('boot_emm.arm') 378 cur_sys.atags_addr = 0x80000100 379 380 # Attach I/O devices that are on chip and also set the appropriate 381 # ranges for the bridge 382 def attachOnChipIO(self, bus, bridge): 383 self.gic.pio = bus.master 384 self.local_cpu_timer.pio = bus.master 385 self.hdlcd.dma = bus.slave 386 # Bridge ranges based on excluding what is part of on-chip I/O 387 # (gic, a9scu) 388 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 389 AddrRange(0x2B000000, size='4MB'), 390 AddrRange(0x30000000, size='256MB'), 391 AddrRange(0x40000000, size='512MB'), 392 AddrRange(0x18000000, size='64MB'), 393 AddrRange(0x1C000000, size='64MB')] 394 395 # Attach I/O devices to specified bus object. Can't do this 396 # earlier, since the bus object itself is typically defined at the 397 # System level. 398 def attachIO(self, bus): 399 self.uart.pio = bus.master 400 self.realview_io.pio = bus.master 401 self.timer0.pio = bus.master 402 self.timer1.pio = bus.master 403 self.clcd.pio = bus.master 404 self.clcd.dma = bus.slave 405 self.hdlcd.pio = bus.master 406 self.kmi0.pio = bus.master 407 self.kmi1.pio = bus.master 408 self.cf_ctrl.pio = bus.master 409 self.cf_ctrl.dma = bus.slave 410 self.cf_ctrl.config = bus.master 411 self.rtc.pio = bus.master 412 bus.use_default_range = True 413 self.vram.port = bus.master 414 self.ide.pio = bus.master 415 self.ide.config = bus.master 416 self.ide.dma = bus.slave 417 self.ethernet.pio = bus.master 418 self.ethernet.config = bus.master 419 self.ethernet.dma = bus.slave 420 self.pciconfig.pio = bus.default 421 422 self.l2x0_fake.pio = bus.master 423 self.uart1_fake.pio = bus.master 424 self.uart2_fake.pio = bus.master 425 self.uart3_fake.pio = bus.master 426 self.sp810_fake.pio = bus.master 427 self.watchdog_fake.pio = bus.master 428 self.aaci_fake.pio = bus.master 429 self.lan_fake.pio = bus.master 430 self.usb_fake.pio = bus.master 431 self.mmc_fake.pio = bus.master 432 433