17635SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 27635SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 37635SBrad.Beckmann@amd.com# All rights reserved. 47635SBrad.Beckmann@amd.com# 57635SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 67635SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 77635SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 87635SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 97635SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 107635SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 117635SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 127635SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 137635SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 147635SBrad.Beckmann@amd.com# this software without specific prior written permission. 157635SBrad.Beckmann@amd.com# 167635SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177635SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187635SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197635SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207635SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217635SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227635SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237635SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247635SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257635SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267635SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277635SBrad.Beckmann@amd.com# 287635SBrad.Beckmann@amd.com# Authors: Ron Dreslinski 297635SBrad.Beckmann@amd.com# Brad Beckmann 307635SBrad.Beckmann@amd.com 3112564Sgabeblack@google.comfrom __future__ import print_function 3213774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 3312564Sgabeblack@google.com 347635SBrad.Beckmann@amd.comimport m5 357635SBrad.Beckmann@amd.comfrom m5.objects import * 367635SBrad.Beckmann@amd.comfrom m5.defines import buildEnv 377635SBrad.Beckmann@amd.comfrom m5.util import addToPath 387635SBrad.Beckmann@amd.comimport os, optparse, sys 3911682Sandreas.hansson@arm.com 4011670Sandreas.hansson@arm.comaddToPath('../') 417635SBrad.Beckmann@amd.com 4211682Sandreas.hansson@arm.comfrom common import Options 4311670Sandreas.hansson@arm.comfrom ruby import Ruby 447635SBrad.Beckmann@amd.com 457635SBrad.Beckmann@amd.com# Get paths we might need. It's expected this file is in m5/configs/example. 467635SBrad.Beckmann@amd.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 477635SBrad.Beckmann@amd.comconfig_root = os.path.dirname(config_path) 487635SBrad.Beckmann@amd.comm5_root = os.path.dirname(config_root) 497635SBrad.Beckmann@amd.com 507635SBrad.Beckmann@amd.comparser = optparse.OptionParser() 5111688Sandreas.hansson@arm.comOptions.addNoISAOptions(parser) 527635SBrad.Beckmann@amd.com 5310083Snilay@cs.wisc.eduparser.add_option("--maxloads", metavar="N", default=100, 5410083Snilay@cs.wisc.edu help="Stop after N loads") 557635SBrad.Beckmann@amd.comparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 567635SBrad.Beckmann@amd.com help="Wakeup every N cycles") 577635SBrad.Beckmann@amd.com 587635SBrad.Beckmann@amd.com# 597635SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options 607635SBrad.Beckmann@amd.com# 617635SBrad.Beckmann@amd.comRuby.define_options(parser) 627635SBrad.Beckmann@amd.com 6313731Sandreas.sandberg@arm.comexec(compile( \ 6413731Sandreas.sandberg@arm.com open(os.path.join(config_root, "common", "Options.py")).read(), \ 6513731Sandreas.sandberg@arm.com os.path.join(config_root, "common", "Options.py"), 'exec')) 667635SBrad.Beckmann@amd.com 677635SBrad.Beckmann@amd.com(options, args) = parser.parse_args() 687635SBrad.Beckmann@amd.com 697635SBrad.Beckmann@amd.com# 707635SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage 717635SBrad.Beckmann@amd.com# races between requests and writebacks. 727635SBrad.Beckmann@amd.com# 737635SBrad.Beckmann@amd.comoptions.l1d_size="256B" 747635SBrad.Beckmann@amd.comoptions.l1i_size="256B" 757635SBrad.Beckmann@amd.comoptions.l2_size="512B" 767635SBrad.Beckmann@amd.comoptions.l3_size="1kB" 777635SBrad.Beckmann@amd.comoptions.l1d_assoc=2 787635SBrad.Beckmann@amd.comoptions.l1i_assoc=2 797635SBrad.Beckmann@amd.comoptions.l2_assoc=2 807635SBrad.Beckmann@amd.comoptions.l3_assoc=2 817635SBrad.Beckmann@amd.com 827635SBrad.Beckmann@amd.comif args: 8312564Sgabeblack@google.com print("Error: script doesn't take any positional arguments") 847635SBrad.Beckmann@amd.com sys.exit(1) 857635SBrad.Beckmann@amd.com 867635SBrad.Beckmann@amd.com# 877635SBrad.Beckmann@amd.com# Create the ruby random tester 887635SBrad.Beckmann@amd.com# 898184Ssomayeh@cs.wisc.edu 908184Ssomayeh@cs.wisc.edu# Check the protocol 918184Ssomayeh@cs.wisc.educheck_flush = False 928184Ssomayeh@cs.wisc.eduif buildEnv['PROTOCOL'] == 'MOESI_hammer': 938184Ssomayeh@cs.wisc.edu check_flush = True 948184Ssomayeh@cs.wisc.edu 958184Ssomayeh@cs.wisc.edutester = RubyTester(check_flush = check_flush, 9610083Snilay@cs.wisc.edu checks_to_complete = options.maxloads, 979108SBrad.Beckmann@amd.com wakeup_frequency = options.wakeup_freq) 987635SBrad.Beckmann@amd.com 997635SBrad.Beckmann@amd.com# 1008931Sandreas.hansson@arm.com# Create the M5 system. Note that the Memory Object isn't 1017635SBrad.Beckmann@amd.com# actually used by the rubytester, but is included to support the 1027635SBrad.Beckmann@amd.com# M5 memory size == Ruby memory size checks 1037635SBrad.Beckmann@amd.com# 10410524Snilay@cs.wisc.edusystem = System(cpu = tester, mem_ranges = [AddrRange(options.mem_size)]) 1059870Sandreas.hansson@arm.com 1069870Sandreas.hansson@arm.com# Create a top-level voltage domain and clock domain 1079870Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 1089870Sandreas.hansson@arm.com 1099870Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 1109870Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 1117635SBrad.Beckmann@amd.com 11210519Snilay@cs.wisc.eduRuby.create_system(options, False, system) 1137635SBrad.Beckmann@amd.com 1149793Sakash.bagdia@arm.com# Create a seperate clock domain for Ruby 1159870Sandreas.hansson@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 1169870Sandreas.hansson@arm.com voltage_domain = system.voltage_domain) 1179793Sakash.bagdia@arm.com 11810120Snilay@cs.wisc.eduassert(options.num_cpus == len(system.ruby._cpu_ports)) 1197635SBrad.Beckmann@amd.com 12010120Snilay@cs.wisc.edutester.num_cpus = len(system.ruby._cpu_ports) 1219108SBrad.Beckmann@amd.com 1227635SBrad.Beckmann@amd.com# 1237635SBrad.Beckmann@amd.com# The tester is most effective when randomization is turned on and 1247635SBrad.Beckmann@amd.com# artifical delay is randomly inserted on messages 1257635SBrad.Beckmann@amd.com# 1267635SBrad.Beckmann@amd.comsystem.ruby.randomization = True 1277635SBrad.Beckmann@amd.com 12810120Snilay@cs.wisc.edufor ruby_port in system.ruby._cpu_ports: 1297635SBrad.Beckmann@amd.com # 1308932SBrad.Beckmann@amd.com # Tie the ruby tester ports to the ruby cpu read and write ports 1317635SBrad.Beckmann@amd.com # 13211266SBrad.Beckmann@amd.com if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: 13311266SBrad.Beckmann@amd.com tester.cpuInstDataPort = ruby_port.slave 13411266SBrad.Beckmann@amd.com elif ruby_port.support_data_reqs: 13511266SBrad.Beckmann@amd.com tester.cpuDataPort = ruby_port.slave 13611266SBrad.Beckmann@amd.com elif ruby_port.support_inst_reqs: 13711266SBrad.Beckmann@amd.com tester.cpuInstPort = ruby_port.slave 13811266SBrad.Beckmann@amd.com 13911266SBrad.Beckmann@amd.com # Do not automatically retry stalled Ruby requests 14011266SBrad.Beckmann@amd.com ruby_port.no_retry_on_stall = True 1417635SBrad.Beckmann@amd.com 1427635SBrad.Beckmann@amd.com # 1437635SBrad.Beckmann@amd.com # Tell each sequencer this is the ruby tester so that it 1447635SBrad.Beckmann@amd.com # copies the subblock back to the checker 1457635SBrad.Beckmann@amd.com # 1467635SBrad.Beckmann@amd.com ruby_port.using_ruby_tester = True 1477635SBrad.Beckmann@amd.com 1487635SBrad.Beckmann@amd.com# ----------------------- 1497635SBrad.Beckmann@amd.com# run simulation 1507635SBrad.Beckmann@amd.com# ----------------------- 1517635SBrad.Beckmann@amd.com 1528801Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system ) 1537635SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing' 1547635SBrad.Beckmann@amd.com 1557635SBrad.Beckmann@amd.com# Not much point in this being higher than the L1 latency 1567635SBrad.Beckmann@amd.comm5.ticks.setGlobalFrequency('1ns') 1577635SBrad.Beckmann@amd.com 1587635SBrad.Beckmann@amd.com# instantiate configuration 1597635SBrad.Beckmann@amd.comm5.instantiate() 1607635SBrad.Beckmann@amd.com 1617635SBrad.Beckmann@amd.com# simulate until program terminates 1629909Snilay@cs.wisc.eduexit_event = m5.simulate(options.abs_max_tick) 1637635SBrad.Beckmann@amd.com 16412564Sgabeblack@google.comprint('Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()) 165