1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Brad Beckmann
29
30import math
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from Ruby import create_topology, create_directories
35from Ruby import send_evicts
36
37#
38# Declare caches used by the protocol
39#
40class L1Cache(RubyCache): pass
41class L2Cache(RubyCache): pass
42
43def define_options(parser):
44    parser.add_option("--l1-retries", type="int", default=1,
45                      help="Token_CMP: # of l1 retries before going persistent")
46    parser.add_option("--timeout-latency", type="int", default=300,
47                      help="Token_CMP: cycles until issuing again");
48    parser.add_option("--disable-dyn-timeouts", action="store_true",
49          help="Token_CMP: disable dyanimc timeouts, use fixed latency instead")
50    parser.add_option("--allow-atomic-migration", action="store_true",
51          help="allow migratory sharing for atomic only accessed blocks")
52
53def create_system(options, full_system, system, dma_ports, bootmem,
54                  ruby_system):
55
56    if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
57        panic("This script requires the MOESI_CMP_token protocol to be built.")
58
59    #
60    # number of tokens that the owner passes to requests so that shared blocks can
61    # respond to read requests
62    #
63    n_tokens = options.num_cpus + 1
64
65    cpu_sequencers = []
66
67    #
68    # The ruby network creation expects the list of nodes in the system to be
69    # consistent with the NetDest list.  Therefore the l1 controller nodes must be
70    # listed before the directory nodes and directory nodes before dma nodes, etc.
71    #
72    l1_cntrl_nodes = []
73    l2_cntrl_nodes = []
74    dma_cntrl_nodes = []
75
76    #
77    # Must create the individual controllers before the network to ensure the
78    # controller constructors are called before the network constructor
79    #
80    l2_bits = int(math.log(options.num_l2caches, 2))
81    block_size_bits = int(math.log(options.cacheline_size, 2))
82
83    for i in range(options.num_cpus):
84        #
85        # First create the Ruby objects associated with this cpu
86        #
87        l1i_cache = L1Cache(size = options.l1i_size,
88                            assoc = options.l1i_assoc,
89                            start_index_bit = block_size_bits)
90        l1d_cache = L1Cache(size = options.l1d_size,
91                            assoc = options.l1d_assoc,
92                            start_index_bit = block_size_bits)
93
94        # the ruby random tester reuses num_cpus to specify the
95        # number of cpu ports connected to the tester object, which
96        # is stored in system.cpu. because there is only ever one
97        # tester object, num_cpus is not necessarily equal to the
98        # size of system.cpu; therefore if len(system.cpu) == 1
99        # we use system.cpu[0] to set the clk_domain, thereby ensuring
100        # we don't index off the end of the cpu list.
101        if len(system.cpu) == 1:
102            clk_domain = system.cpu[0].clk_domain
103        else:
104            clk_domain = system.cpu[i].clk_domain
105
106        l1_cntrl = L1Cache_Controller(version=i, L1Icache=l1i_cache,
107                                      L1Dcache=l1d_cache,
108                                      l2_select_num_bits=l2_bits,
109                                      N_tokens=n_tokens,
110                                      retry_threshold=options.l1_retries,
111                                      fixed_timeout_latency=\
112                                      options.timeout_latency,
113                                      dynamic_timeout_enabled=\
114                                      not options.disable_dyn_timeouts,
115                                      no_mig_atomic=not \
116                                      options.allow_atomic_migration,
117                                      send_evictions=send_evicts(options),
118                                      transitions_per_cycle=options.ports,
119                                      clk_domain=clk_domain,
120                                      ruby_system=ruby_system)
121
122        cpu_seq = RubySequencer(version=i, icache=l1i_cache,
123                                dcache=l1d_cache, clk_domain=clk_domain,
124                                ruby_system=ruby_system)
125
126        l1_cntrl.sequencer = cpu_seq
127        exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
128
129        # Add controllers and sequencers to the appropriate lists
130        cpu_sequencers.append(cpu_seq)
131        l1_cntrl_nodes.append(l1_cntrl)
132
133        # Connect the L1 controllers and the network
134        l1_cntrl.requestFromL1Cache = MessageBuffer()
135        l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
136        l1_cntrl.responseFromL1Cache = MessageBuffer()
137        l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
138        l1_cntrl.persistentFromL1Cache = MessageBuffer(ordered = True)
139        l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave
140
141        l1_cntrl.mandatoryQueue = MessageBuffer()
142        l1_cntrl.requestToL1Cache = MessageBuffer()
143        l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
144        l1_cntrl.responseToL1Cache = MessageBuffer()
145        l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
146        l1_cntrl.persistentToL1Cache = MessageBuffer(ordered = True)
147        l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master
148
149
150    l2_index_start = block_size_bits + l2_bits
151
152    for i in range(options.num_l2caches):
153        #
154        # First create the Ruby objects associated with this cpu
155        #
156        l2_cache = L2Cache(size = options.l2_size,
157                           assoc = options.l2_assoc,
158                           start_index_bit = l2_index_start)
159
160        l2_cntrl = L2Cache_Controller(version = i,
161                                      L2cache = l2_cache,
162                                      N_tokens = n_tokens,
163                                      transitions_per_cycle = options.ports,
164                                      ruby_system = ruby_system)
165
166        exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
167        l2_cntrl_nodes.append(l2_cntrl)
168
169        # Connect the L2 controllers and the network
170        l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer()
171        l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
172        l2_cntrl.L1RequestFromL2Cache = MessageBuffer()
173        l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
174        l2_cntrl.responseFromL2Cache = MessageBuffer()
175        l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
176
177        l2_cntrl.GlobalRequestToL2Cache = MessageBuffer()
178        l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
179        l2_cntrl.L1RequestToL2Cache = MessageBuffer()
180        l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
181        l2_cntrl.responseToL2Cache = MessageBuffer()
182        l2_cntrl.responseToL2Cache.slave = ruby_system.network.master
183        l2_cntrl.persistentToL2Cache = MessageBuffer(ordered = True)
184        l2_cntrl.persistentToL2Cache.slave = ruby_system.network.master
185
186
187    # Run each of the ruby memory controllers at a ratio of the frequency of
188    # the ruby system
189    # clk_divider value is a fix to pass regression.
190    ruby_system.memctrl_clk_domain = DerivedClockDomain(
191                                          clk_domain=ruby_system.clk_domain,
192                                          clk_divider=3)
193
194    mem_dir_cntrl_nodes, rom_dir_cntrl_node = create_directories(
195        options, bootmem, ruby_system, system)
196    dir_cntrl_nodes = mem_dir_cntrl_nodes[:]
197    if rom_dir_cntrl_node is not None:
198        dir_cntrl_nodes.append(rom_dir_cntrl_node)
199    for dir_cntrl in dir_cntrl_nodes:
200        dir_cntrl.l2_select_num_bits = l2_bits
201        # Connect the directory controllers and the network
202        dir_cntrl.requestToDir = MessageBuffer()
203        dir_cntrl.requestToDir.slave = ruby_system.network.master
204        dir_cntrl.responseToDir = MessageBuffer()
205        dir_cntrl.responseToDir.slave = ruby_system.network.master
206        dir_cntrl.persistentToDir = MessageBuffer(ordered = True)
207        dir_cntrl.persistentToDir.slave = ruby_system.network.master
208        dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
209        dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
210
211        dir_cntrl.requestFromDir = MessageBuffer()
212        dir_cntrl.requestFromDir.master = ruby_system.network.slave
213        dir_cntrl.responseFromDir = MessageBuffer()
214        dir_cntrl.responseFromDir.master = ruby_system.network.slave
215        dir_cntrl.persistentFromDir = MessageBuffer(ordered = True)
216        dir_cntrl.persistentFromDir.master = ruby_system.network.slave
217        dir_cntrl.dmaResponseFromDir = MessageBuffer(ordered = True)
218        dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
219        dir_cntrl.responseFromMemory = MessageBuffer()
220
221
222    for i, dma_port in enumerate(dma_ports):
223        #
224        # Create the Ruby objects associated with the dma controller
225        #
226        dma_seq = DMASequencer(version = i,
227                               ruby_system = ruby_system,
228                               slave = dma_port)
229
230        dma_cntrl = DMA_Controller(version = i,
231                                   dma_sequencer = dma_seq,
232                                   transitions_per_cycle = options.ports,
233                                   ruby_system = ruby_system)
234
235        exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
236        dma_cntrl_nodes.append(dma_cntrl)
237
238        # Connect the dma controller to the network
239        dma_cntrl.mandatoryQueue = MessageBuffer()
240        dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
241        dma_cntrl.responseFromDir.slave = ruby_system.network.master
242        dma_cntrl.reqToDirectory = MessageBuffer()
243        dma_cntrl.reqToDirectory.master = ruby_system.network.slave
244
245    all_cntrls = l1_cntrl_nodes + \
246                 l2_cntrl_nodes + \
247                 dir_cntrl_nodes + \
248                 dma_cntrl_nodes
249
250    # Create the io controller and the sequencer
251    if full_system:
252        io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
253        ruby_system._io_port = io_seq
254        io_controller = DMA_Controller(version = len(dma_ports),
255                                       dma_sequencer = io_seq,
256                                       ruby_system = ruby_system)
257        ruby_system.io_controller = io_controller
258
259        # Connect the dma controller to the network
260        io_controller.mandatoryQueue = MessageBuffer()
261        io_controller.responseFromDir = MessageBuffer(ordered = True)
262        io_controller.responseFromDir.slave = ruby_system.network.master
263        io_controller.reqToDirectory = MessageBuffer()
264        io_controller.reqToDirectory.master = ruby_system.network.slave
265
266        all_cntrls = all_cntrls + [io_controller]
267
268    ruby_system.network.number_of_virtual_networks = 6
269    topology = create_topology(all_cntrls, options)
270    return (cpu_sequencers, mem_dir_cntrl_nodes, topology)
271