16928SBrad.Beckmann@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
26928SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
36928SBrad.Beckmann@amd.com# All rights reserved.
46928SBrad.Beckmann@amd.com#
56928SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without
66928SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are
76928SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright
86928SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer;
96928SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright
106928SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the
116928SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution;
126928SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its
136928SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from
146928SBrad.Beckmann@amd.com# this software without specific prior written permission.
156928SBrad.Beckmann@amd.com#
166928SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176928SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186928SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196928SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206928SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216928SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226928SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236928SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246928SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256928SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266928SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276928SBrad.Beckmann@amd.com#
286928SBrad.Beckmann@amd.com# Authors: Ron Dreslinski
296928SBrad.Beckmann@amd.com#          Brad Beckmann
306928SBrad.Beckmann@amd.com
316928SBrad.Beckmann@amd.comimport m5
326928SBrad.Beckmann@amd.comfrom m5.objects import *
336928SBrad.Beckmann@amd.comfrom m5.defines import buildEnv
346928SBrad.Beckmann@amd.comfrom m5.util import addToPath
356928SBrad.Beckmann@amd.comimport os, optparse, sys
366928SBrad.Beckmann@amd.com
3711670Sandreas.hansson@arm.comm5.util.addToPath('../configs/')
386928SBrad.Beckmann@amd.com
3911670Sandreas.hansson@arm.comfrom ruby import Ruby
4011682Sandreas.hansson@arm.comfrom common import Options
416928SBrad.Beckmann@amd.com
426928SBrad.Beckmann@amd.comparser = optparse.OptionParser()
4311706Sandreas.hansson@arm.comOptions.addNoISAOptions(parser)
446928SBrad.Beckmann@amd.com
457570SBrad.Beckmann@amd.com# Add the ruby specific and protocol specific options
467570SBrad.Beckmann@amd.comRuby.define_options(parser)
476928SBrad.Beckmann@amd.com
486928SBrad.Beckmann@amd.com(options, args) = parser.parse_args()
496928SBrad.Beckmann@amd.com
506928SBrad.Beckmann@amd.com#
517570SBrad.Beckmann@amd.com# Set the default cache size and associativity to be very small to encourage
527570SBrad.Beckmann@amd.com# races between requests and writebacks.
537570SBrad.Beckmann@amd.com#
547570SBrad.Beckmann@amd.comoptions.l1d_size="256B"
557570SBrad.Beckmann@amd.comoptions.l1i_size="256B"
567570SBrad.Beckmann@amd.comoptions.l2_size="512B"
577570SBrad.Beckmann@amd.comoptions.l3_size="1kB"
587570SBrad.Beckmann@amd.comoptions.l1d_assoc=2
597570SBrad.Beckmann@amd.comoptions.l1i_assoc=2
607570SBrad.Beckmann@amd.comoptions.l2_assoc=2
617570SBrad.Beckmann@amd.comoptions.l3_assoc=2
629841Snilay@cs.wisc.eduoptions.ports=32
637570SBrad.Beckmann@amd.com
648933SBrad.Beckmann@amd.com# Turn on flush check for the hammer protocol
658933SBrad.Beckmann@amd.comcheck_flush = False
668933SBrad.Beckmann@amd.comif buildEnv['PROTOCOL'] == 'MOESI_hammer':
678933SBrad.Beckmann@amd.com    check_flush = True
688933SBrad.Beckmann@amd.com
697570SBrad.Beckmann@amd.com#
706928SBrad.Beckmann@amd.com# create the tester and system, including ruby
716928SBrad.Beckmann@amd.com#
728933SBrad.Beckmann@amd.comtester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
738940SBrad.Beckmann@amd.com                    wakeup_frequency = 10, num_cpus = options.num_cpus)
746928SBrad.Beckmann@amd.com
7510300Scastilloe@unican.es# We set the testers as cpu for ruby to find the correct clock domains
7610300Scastilloe@unican.es# for the L1 Objects.
7710524Snilay@cs.wisc.edusystem = System(cpu = tester)
7810300Scastilloe@unican.es
799827Sakash.bagdia@arm.com# Dummy voltage domain for all our clock domains
809827Sakash.bagdia@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
819827Sakash.bagdia@arm.comsystem.clk_domain = SrcClockDomain(clock = '1GHz',
829827Sakash.bagdia@arm.com                                   voltage_domain = system.voltage_domain)
836928SBrad.Beckmann@amd.com
849826Sandreas.hansson@arm.comsystem.mem_ranges = AddrRange('256MB')
859826Sandreas.hansson@arm.com
8610519Snilay@cs.wisc.eduRuby.create_system(options, False, system)
876928SBrad.Beckmann@amd.com
889793Sakash.bagdia@arm.com# Create a separate clock domain for Ruby
899827Sakash.bagdia@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
909827Sakash.bagdia@arm.com                                        voltage_domain = system.voltage_domain)
919793Sakash.bagdia@arm.com
9210120Snilay@cs.wisc.eduassert(options.num_cpus == len(system.ruby._cpu_ports))
936928SBrad.Beckmann@amd.com
9411267SBrad.Beckmann@amd.comtester.num_cpus = len(system.ruby._cpu_ports)
9511267SBrad.Beckmann@amd.com
966928SBrad.Beckmann@amd.com#
976928SBrad.Beckmann@amd.com# The tester is most effective when randomization is turned on and
986928SBrad.Beckmann@amd.com# artifical delay is randomly inserted on messages
996928SBrad.Beckmann@amd.com#
1006928SBrad.Beckmann@amd.comsystem.ruby.randomization = True
1016928SBrad.Beckmann@amd.com
10210120Snilay@cs.wisc.edufor ruby_port in system.ruby._cpu_ports:
1036928SBrad.Beckmann@amd.com    #
1048940SBrad.Beckmann@amd.com    # Tie the ruby tester ports to the ruby cpu read and write ports
1056928SBrad.Beckmann@amd.com    #
10611267SBrad.Beckmann@amd.com    if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
10711267SBrad.Beckmann@amd.com        tester.cpuInstDataPort = ruby_port.slave
10811267SBrad.Beckmann@amd.com    elif ruby_port.support_data_reqs:
10911267SBrad.Beckmann@amd.com        tester.cpuDataPort = ruby_port.slave
11011267SBrad.Beckmann@amd.com    elif ruby_port.support_inst_reqs:
11111267SBrad.Beckmann@amd.com        tester.cpuInstPort = ruby_port.slave
11211267SBrad.Beckmann@amd.com
11311267SBrad.Beckmann@amd.com    # Do not automatically retry stalled Ruby requests
11411267SBrad.Beckmann@amd.com    ruby_port.no_retry_on_stall = True
1156928SBrad.Beckmann@amd.com
1166928SBrad.Beckmann@amd.com    #
1176928SBrad.Beckmann@amd.com    # Tell the sequencer this is the ruby tester so that it
1186928SBrad.Beckmann@amd.com    # copies the subblock back to the checker
1196928SBrad.Beckmann@amd.com    #
1206928SBrad.Beckmann@amd.com    ruby_port.using_ruby_tester = True
1216928SBrad.Beckmann@amd.com
1226928SBrad.Beckmann@amd.com# -----------------------
1236928SBrad.Beckmann@amd.com# run simulation
1246928SBrad.Beckmann@amd.com# -----------------------
1256928SBrad.Beckmann@amd.com
1268801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system )
1276928SBrad.Beckmann@amd.comroot.system.mem_mode = 'timing'
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