1# -*- coding: utf-8 -*-
2# Copyright (c) 2017 Jason Power
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Jason Power
29
30""" This file creates a set of Ruby caches, the Ruby network, and a simple
31point-to-point topology.
32See Part 3 in the Learning gem5 book: learning.gem5.org/book/part3
33
34IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
35           also needs to be updated. For now, email Jason <jason@lowepower.com>
36
37"""
38
39from __future__ import print_function
40from __future__ import absolute_import
41
42import math
43
44from m5.defines import buildEnv
45from m5.util import fatal, panic
46
47from m5.objects import *
48
49class MyCacheSystem(RubySystem):
50
51    def __init__(self):
52        if buildEnv['PROTOCOL'] != 'MSI':
53            fatal("This system assumes MSI from learning gem5!")
54
55        super(MyCacheSystem, self).__init__()
56
57    def setup(self, system, cpus, mem_ctrls):
58        """Set up the Ruby cache subsystem. Note: This can't be done in the
59           constructor because many of these items require a pointer to the
60           ruby system (self). This causes infinite recursion in initialize()
61           if we do this in the __init__.
62        """
63        # Ruby's global network.
64        self.network = MyNetwork(self)
65
66        # MSI uses 3 virtual networks. One for requests (lowest priority), one
67        # for responses (highest priority), and one for "forwards" or
68        # cache-to-cache requests. See *.sm files for details.
69        self.number_of_virtual_networks = 3
70        self.network.number_of_virtual_networks = 3
71
72        # There is a single global list of all of the controllers to make it
73        # easier to connect everything to the global network. This can be
74        # customized depending on the topology/network requirements.
75        # Create one controller for each L1 cache (and the cache mem obj.)
76        # Create a single directory controller (Really the memory cntrl)
77        self.controllers = \
78            [L1Cache(system, self, cpu) for cpu in cpus] + \
79            [DirController(self, system.mem_ranges, mem_ctrls)]
80
81        # Create one sequencer per CPU. In many systems this is more
82        # complicated since you have to create sequencers for DMA controllers
83        # and other controllers, too.
84        self.sequencers = [RubySequencer(version = i,
85                                # I/D cache is combined and grab from ctrl
86                                icache = self.controllers[i].cacheMemory,
87                                dcache = self.controllers[i].cacheMemory,
88                                clk_domain = self.controllers[i].clk_domain,
89                                ) for i in range(len(cpus))]
90
91        # We know that we put the controllers in an order such that the first
92        # N of them are the L1 caches which need a sequencer pointer
93        for i,c in enumerate(self.controllers[0:len(self.sequencers)]):
94            c.sequencer = self.sequencers[i]
95
96        self.num_of_sequencers = len(self.sequencers)
97
98        # Create the network and connect the controllers.
99        # NOTE: This is quite different if using Garnet!
100        self.network.connectControllers(self.controllers)
101        self.network.setup_buffers()
102
103        # Set up a proxy port for the system_port. Used for load binaries and
104        # other functional-only things.
105        self.sys_port_proxy = RubyPortProxy()
106        system.system_port = self.sys_port_proxy.slave
107
108        # Connect the cpu's cache, interrupt, and TLB ports to Ruby
109        for i,cpu in enumerate(cpus):
110            cpu.icache_port = self.sequencers[i].slave
111            cpu.dcache_port = self.sequencers[i].slave
112            isa = buildEnv['TARGET_ISA']
113            if isa == 'x86':
114                cpu.interrupts[0].pio = self.sequencers[i].master
115                cpu.interrupts[0].int_master = self.sequencers[i].slave
116                cpu.interrupts[0].int_slave = self.sequencers[i].master
117            if isa == 'x86' or isa == 'arm':
118                cpu.itb.walker.port = self.sequencers[i].slave
119                cpu.dtb.walker.port = self.sequencers[i].slave
120
121
122class L1Cache(L1Cache_Controller):
123
124    _version = 0
125    @classmethod
126    def versionCount(cls):
127        cls._version += 1 # Use count for this particular type
128        return cls._version - 1
129
130    def __init__(self, system, ruby_system, cpu):
131        """CPUs are needed to grab the clock domain and system is needed for
132           the cache block size.
133        """
134        super(L1Cache, self).__init__()
135
136        self.version = self.versionCount()
137        # This is the cache memory object that stores the cache data and tags
138        self.cacheMemory = RubyCache(size = '16kB',
139                               assoc = 8,
140                               start_index_bit = self.getBlockSizeBits(system))
141        self.clk_domain = cpu.clk_domain
142        self.send_evictions = self.sendEvicts(cpu)
143        self.ruby_system = ruby_system
144        self.connectQueues(ruby_system)
145
146    def getBlockSizeBits(self, system):
147        bits = int(math.log(system.cache_line_size, 2))
148        if 2**bits != system.cache_line_size.value:
149            panic("Cache line size not a power of 2!")
150        return bits
151
152    def sendEvicts(self, cpu):
153        """True if the CPU model or ISA requires sending evictions from caches
154           to the CPU. Two scenarios warrant forwarding evictions to the CPU:
155           1. The O3 model must keep the LSQ coherent with the caches
156           2. The x86 mwait instruction is built on top of coherence
157           3. The local exclusive monitor in ARM systems
158        """
159        if type(cpu) is DerivO3CPU or \
160           buildEnv['TARGET_ISA'] in ('x86', 'arm'):
161            return True
162        return False
163
164    def connectQueues(self, ruby_system):
165        """Connect all of the queues for this controller.
166        """
167        # mandatoryQueue is a special variable. It is used by the sequencer to
168        # send RubyRequests from the CPU (or other processor). It isn't
169        # explicitly connected to anything.
170        self.mandatoryQueue = MessageBuffer()
171
172        # All message buffers must be created and connected to the general
173        # Ruby network. In this case, "slave/master" don't mean the same thing
174        # as normal gem5 ports. If a MessageBuffer is a "to" buffer (i.e., out)
175        # then you use the "master", otherwise, the slave.
176        self.requestToDir = MessageBuffer(ordered = True)
177        self.requestToDir.master = ruby_system.network.slave
178        self.responseToDirOrSibling = MessageBuffer(ordered = True)
179        self.responseToDirOrSibling.master = ruby_system.network.slave
180        self.forwardFromDir = MessageBuffer(ordered = True)
181        self.forwardFromDir.slave = ruby_system.network.master
182        self.responseFromDirOrSibling = MessageBuffer(ordered = True)
183        self.responseFromDirOrSibling.slave = ruby_system.network.master
184
185class DirController(Directory_Controller):
186
187    _version = 0
188    @classmethod
189    def versionCount(cls):
190        cls._version += 1 # Use count for this particular type
191        return cls._version - 1
192
193    def __init__(self, ruby_system, ranges, mem_ctrls):
194        """ranges are the memory ranges assigned to this controller.
195        """
196        if len(mem_ctrls) > 1:
197            panic("This cache system can only be connected to one mem ctrl")
198        super(DirController, self).__init__()
199        self.version = self.versionCount()
200        self.addr_ranges = ranges
201        self.ruby_system = ruby_system
202        self.directory = RubyDirectoryMemory()
203        # Connect this directory to the memory side.
204        self.memory = mem_ctrls[0].port
205        self.connectQueues(ruby_system)
206
207    def connectQueues(self, ruby_system):
208        self.requestFromCache = MessageBuffer(ordered = True)
209        self.requestFromCache.slave = ruby_system.network.master
210        self.responseFromCache = MessageBuffer(ordered = True)
211        self.responseFromCache.slave = ruby_system.network.master
212
213        self.responseToCache = MessageBuffer(ordered = True)
214        self.responseToCache.master = ruby_system.network.slave
215        self.forwardToCache = MessageBuffer(ordered = True)
216        self.forwardToCache.master = ruby_system.network.slave
217
218        # This is another special message buffer. It is used to send replies
219        # from memory back to the controller. Any messages received on the
220        # memory port (see self.memory above) will be directed to this
221        # message buffer.
222        self.responseFromMemory = MessageBuffer()
223
224class MyNetwork(SimpleNetwork):
225    """A simple point-to-point network. This doesn't not use garnet.
226    """
227
228    def __init__(self, ruby_system):
229        super(MyNetwork, self).__init__()
230        self.netifs = []
231        self.ruby_system = ruby_system
232
233    def connectControllers(self, controllers):
234        """Connect all of the controllers to routers and connec the routers
235           together in a point-to-point network.
236        """
237        # Create one router/switch per controller in the system
238        self.routers = [Switch(router_id = i) for i in range(len(controllers))]
239
240        # Make a link from each controller to the router. The link goes
241        # externally to the network.
242        self.ext_links = [SimpleExtLink(link_id=i, ext_node=c,
243                                        int_node=self.routers[i])
244                          for i, c in enumerate(controllers)]
245
246        # Make an "internal" link (internal to the network) between every pair
247        # of routers.
248        link_count = 0
249        self.int_links = []
250        for ri in self.routers:
251            for rj in self.routers:
252                if ri == rj: continue # Don't connect a router to itself!
253                link_count += 1
254                self.int_links.append(SimpleIntLink(link_id = link_count,
255                                                    src_node = ri,
256                                                    dst_node = rj))
257