/gem5/src/arch/x86/ |
H A D | X86LocalApic.py | 63 clk_domain = DerivedClockDomain( variable in class:X86LocalApic 64 clk_domain=Parent.clk_domain, clk_divider=16)
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/gem5/src/sim/ |
H A D | ClockedObject.py | 67 clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain") variable in class:ClockedObject
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H A D | DVFSHandler.py | 56 sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain,
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H A D | ClockDomain.py | 80 clk_domain = Param.ClockDomain("Parent clock domain") variable in class:DerivedClockDomain
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/gem5/tests/configs/ |
H A D | simple-atomic-mp-ruby.py | 40 clk_domain = SrcClockDomain(clock = '1GHz')) variable 44 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 50 cpu.clk_domain = system.cpu_clk_domain
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H A D | o3-timing-ruby.py | 41 clk_domain = SrcClockDomain(clock = '1GHz')) variable 45 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
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H A D | memtest.py | 44 system.clk_domain = SrcClockDomain(clock = '1GHz', 52 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) 53 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 62 cpu.clk_domain = system.cpu_clk_domain
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H A D | memtest-filter.py | 44 system.clk_domain = SrcClockDomain(clock = '1GHz', 52 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain, 54 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 63 cpu.clk_domain = system.cpu_clk_domain
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H A D | twosys-tsunami-simple-atomic.py | 42 test_sys.clk_domain = SrcClockDomain(clock = '1GHz', 52 test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 57 test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', 77 drive_sys.clk_domain = SrcClockDomain(clock = '1GHz', 87 drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz', 92 drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz',
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H A D | o3-timing-mp-ruby.py | 41 clk_domain = SrcClockDomain(clock = '1GHz')) variable 52 cpu.clk_domain = system.cpu_clk_domain
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H A D | t1000-simple-atomic.py | 40 system.clk_domain = SrcClockDomain(clock = '1GHz', 44 cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
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H A D | simple-timing-ruby.py | 68 system.clk_domain = SrcClockDomain(clock = '1GHz', 73 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 80 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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H A D | simple-timing-mp-ruby.py | 68 system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz')) 72 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 77 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
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H A D | memtest-ruby.py | 78 system.clk_domain = SrcClockDomain(clock = '1GHz', 88 cpu.clk_domain = system.cpu_clk_domain 95 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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/gem5/configs/learning_gem5/part3/ |
H A D | ruby_test.py | 51 system.clk_domain = SrcClockDomain() 52 system.clk_domain.clock = '1GHz' 53 system.clk_domain.voltage_domain = VoltageDomain()
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H A D | simple_ruby.py | 60 system.clk_domain = SrcClockDomain() 61 system.clk_domain.clock = '1GHz' 62 system.clk_domain.voltage_domain = VoltageDomain()
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/gem5/tests/gem5/memory/ |
H A D | memtest-run.py | 45 system.clk_domain = SrcClockDomain(clock = '1GHz', 53 system.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) 54 system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 63 cpu.clk_domain = system.cpu_clk_domain
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/gem5/configs/ruby/ |
H A D | MI_example.py | 83 # we use system.cpu[0] to set the clk_domain, thereby ensuring 86 clk_domain = system.cpu[0].clk_domain 88 clk_domain = system.cpu[i].clk_domain 94 clk_domain=clk_domain, 98 clk_domain=clk_domain, ruby_system=ruby_system) 126 clk_domain [all...] |
H A D | MESI_Two_Level.py | 90 # we use system.cpu[0] to set the clk_domain, thereby ensuring 93 clk_domain = system.cpu[0].clk_domain 95 clk_domain = system.cpu[i].clk_domain 103 clk_domain = clk_domain, 108 dcache = l1d_cache, clk_domain = clk_domain, 174 clk_domain [all...] |
H A D | MOESI_CMP_directory.py | 104 # we use system.cpu[0] to set the clk_domain, thereby ensuring 107 clk_domain = system.cpu[0].clk_domain 109 clk_domain = system.cpu[i].clk_domain 115 clk_domain=clk_domain, 119 dcache=l1d_cache, clk_domain=clk_domain, 195 clk_domain [all...] |
/gem5/configs/learning_gem5/part1/ |
H A D | simple.py | 53 system.clk_domain = SrcClockDomain() 54 system.clk_domain.clock = '1GHz' 55 system.clk_domain.voltage_domain = VoltageDomain()
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/gem5/configs/learning_gem5/part2/ |
H A D | simple_cache.py | 48 system.clk_domain = SrcClockDomain() 49 system.clk_domain.clock = '1GHz' 50 system.clk_domain.voltage_domain = VoltageDomain()
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H A D | simple_memobj.py | 48 system.clk_domain = SrcClockDomain() 49 system.clk_domain.clock = '1GHz' 50 system.clk_domain.voltage_domain = VoltageDomain()
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/gem5/src/arch/alpha/ |
H A D | AlphaSystem.py | 49 boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock[0]
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/gem5/configs/example/arm/ |
H A D | devices.py | 125 self.clk_domain = SrcClockDomain(clock=cpu_clock, 129 clk_domain=self.clk_domain) 152 def addL2(self, clk_domain): 155 self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) 194 self.clk_domain = SrcClockDomain(clock="1GHz", 277 cluster.addL2(cluster.clk_domain) 280 key=lambda c: c.clk_domain.clock[0]) 281 self.l3 = L3(clk_domain [all...] |