Searched refs:TLB (Results 1 - 25 of 37) sorted by relevance

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/gem5/src/arch/arm/
H A Dstage2_lookup.hh55 class TLB;
61 TLB *stage1Tlb;
62 TLB *stage2Tlb;
65 TLB::Translation *transState;
69 TLB::ArmTranslationType tranType;
77 Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req,
78 TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing,
79 bool _functional, TLB::ArmTranslationType _tranType) :
H A Dvtophys.cc71 // Set up a functional memory Request to pass to the TLB
74 ArmISA::TLB *tlb;
83 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
84 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
88 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
89 fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
H A Dstage2_mmu.hh55 TLB *_stage1Tlb;
56 /** The TLB that will cache the stage 2 look ups. */
57 TLB *_stage2Tlb;
121 TLB* stage1Tlb() const { return _stage1Tlb; }
122 TLB* stage2Tlb() const { return _stage2Tlb; }
H A Dtlb.cc65 #include "debug/TLB.hh"
76 TLB::TLB(const ArmTLBParams *p) function in class:TLB
98 TLB::~TLB()
104 TLB::init()
111 TLB::setMMU(Stage2MMU *m, MasterID master_id)
118 TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
136 TLB::finalizePhysical(const RequestPtr &req,
152 TLB
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H A Disa.cc1108 // TLB Invalidate All
1118 // TLB Invalidate All, Inner Shareable
1128 // Instruction TLB Invalidate All
1138 // Data TLB Invalidate All
1148 // TLB Invalidate by VA
1166 // TLB Invalidate by VA, Inner Shareable
1181 // TLB Invalidate by ASID match
1194 // TLB Invalidate by ASID match, Inner Shareable
1210 // TLB Invalidate by VA, All ASID
1223 // TLB Invalidat
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H A Dtlb.hh64 class TLB;
73 * Check if a TLB translation should be forced to fail.
102 class TLB : public BaseTLB class in namespace:ArmISA
152 int size; // TLB Size
153 bool isStage2; // Indicates this TLB is part of the second stage MMU
159 uint64_t _attr; // Memory attributes for last accessed TLB entry
161 // be routed directly to the stage 2 TLB
164 TLB *stage2Tlb;
194 /** PMU probe for TLB refills */
200 TLB(cons
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H A Dtable_walker.cc52 #include "debug/TLB.hh"
114 fatal_if(!tlb, "Table walker must have a valid TLB\n");
140 mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc),
191 uint8_t _vmid, bool _isHyp, TLB::Mode _mode,
192 TLB::Translation *_trans, bool _timing, bool _functional,
193 bool secure, TLB::ArmTranslationType tranType,
203 // once per TLB. For timing mode, a new instance is generated for every
204 // TLB miss.
241 TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType);
259 the TLB, al
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/gem5/src/arch/mips/
H A Dtlb.cc50 #include "debug/TLB.hh"
60 // MIPS TLB
63 TLB::TLB(const Params *p) function in class:TLB
71 TLB::~TLB()
77 // look up an entry in the TLB
79 TLB::lookup(Addr vpn, uint8_t asn) const
89 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
103 DPRINTF(TLB, "looku
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H A Dtlb.hh52 /* MIPS does not distinguish between a DTLB and an ITLB -> unified TLB
54 simply create an ITLB and DTLB that will point to the real TLB */
57 class TLB : public BaseTLB class in namespace:MipsISA
64 int size; // TLB Size
84 TLB(const Params *p);
88 virtual ~TLB();
/gem5/src/arch/power/
H A Dtlb.cc51 #include "debug/TLB.hh"
62 // POWER TLB
67 TLB::TLB(const Params *p) function in class:TLB
75 TLB::~TLB()
81 // look up an entry in the TLB
83 TLB::lookup(Addr vpn, uint8_t asn) const
106 DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
112 TLB
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H A Dtlb.hh99 class TLB : public BaseTLB class in namespace:PowerISA
106 int size; // TLB Size
133 TLB(const Params *p);
134 virtual ~TLB();
/gem5/src/arch/sparc/
H A Dmmapped_ipr.hh54 return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegRead(xc, pkt);
63 return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegWrite(xc, pkt);
H A Dvtophys.cc86 TLB* itb = dynamic_cast<TLB *>(tc->getITBPtr());
87 TLB* dtb = dynamic_cast<TLB *>(tc->getDTBPtr());
128 DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr,
H A Dtlb.cc45 #include "debug/TLB.hh"
55 TLB::TLB(const Params *p) function in class:SparcISA::TLB
61 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
83 TLB::clearUsedBits()
97 TLB::insert(Addr va, int partition_id, int context_id, bool real,
114 DPRINTF(TLB,
115 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
128 DPRINTF(TLB, "TL
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/gem5/src/arch/x86/
H A Dtlb.cc54 #include "debug/TLB.hh"
62 TLB::TLB(const Params *p) function in class:X86ISA::TLB
79 TLB::evictLRU()
97 TLB::insert(Addr vpn, const TlbEntry &entry)
121 TLB::lookup(Addr va, bool update_lru)
130 TLB::flushAll()
132 DPRINTF(TLB, "Invalidating all entries.\n");
143 TLB::setConfigAddress(uint32_t addr)
149 TLB
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H A Dvtophys.cc63 Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker();
H A Dtlb.hh58 class TLB : public BaseTLB class in namespace:X86ISA
70 TLB(const Params *p);
H A Dpagetable_walker.hh108 TLB::Translation * translation;
170 // The TLB we're supposed to load.
171 TLB * tlb;
193 void setTLB(TLB * _tlb)
H A Disa.cc219 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
220 dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
236 dynamic_cast<TLB *>(tc->getITBPtr())->flushNonGlobal();
237 dynamic_cast<TLB *>(tc->getDTBPtr())->flushNonGlobal();
243 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
244 dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
/gem5/src/arch/riscv/
H A Dtlb.cc51 #include "debug/TLB.hh"
62 // RISC-V TLB
65 TLB::TLB(const Params *p) function in class:TLB
73 TLB::~TLB()
79 // look up an entry in the TLB
81 TLB::lookup(Addr vpn, uint8_t asn) const
91 /* 1KB TLB Lookup code - from MIPS ARM Volume III - Rev. 2.50 */
105 DPRINTF(TLB, "looku
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H A Dtlb.hh53 simply create an ITLB and DTLB that will point to the real TLB */
56 class TLB : public BaseTLB class in namespace:RiscvISA
63 int size; // TLB Size
83 TLB(const Params *p);
87 virtual ~TLB();
/gem5/src/arch/arm/insts/
H A Dsve_mem.hh66 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
91 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
117 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
143 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
/gem5/src/arch/alpha/
H A Dtlb.cc47 #include "debug/TLB.hh"
56 // Alpha TLB
66 TLB::TLB(const Params *p) function in class:AlphaISA::TLB
72 TLB::~TLB()
77 TLB::regStats()
162 // look up an entry in the TLB
164 TLB::lookup(Addr vpn, uint8_t asn)
200 DPRINTF(TLB, "looku
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H A Dtlb.hh53 class TLB : public BaseTLB class in namespace:AlphaISA
85 TLB(const Params *p);
86 virtual ~TLB();
/gem5/src/arch/arm/tracers/
H A Dtarmac_record_v8.cc59 ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
73 ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());

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