16019Shines@cs.fsu.edu/*
210037SARM gem5 Developers * Copyright (c) 2010, 2012-2013 ARM Limited
37694SAli.Saidi@ARM.com * All rights reserved
47694SAli.Saidi@ARM.com *
57694SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67694SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77694SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87694SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97694SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107694SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117694SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127694SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137694SAli.Saidi@ARM.com *
146019Shines@cs.fsu.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University
166019Shines@cs.fsu.edu * All rights reserved.
176019Shines@cs.fsu.edu *
186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
276019Shines@cs.fsu.edu * this software without specific prior written permission.
286019Shines@cs.fsu.edu *
296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406019Shines@cs.fsu.edu *
416019Shines@cs.fsu.edu * Authors: Ali Saidi
426019Shines@cs.fsu.edu *          Nathan Binkert
436019Shines@cs.fsu.edu *          Stephen Hines
446019Shines@cs.fsu.edu */
456019Shines@cs.fsu.edu
4611793Sbrandon.potter@amd.com#include "arch/arm/vtophys.hh"
4711793Sbrandon.potter@amd.com
486019Shines@cs.fsu.edu#include <string>
496019Shines@cs.fsu.edu
5010037SARM gem5 Developers#include "arch/arm/faults.hh"
517694SAli.Saidi@ARM.com#include "arch/arm/table_walker.hh"
527694SAli.Saidi@ARM.com#include "arch/arm/tlb.hh"
536019Shines@cs.fsu.edu#include "base/chunk_generator.hh"
546019Shines@cs.fsu.edu#include "base/trace.hh"
556019Shines@cs.fsu.edu#include "cpu/thread_context.hh"
568706Sandreas.hansson@arm.com#include "mem/fs_translating_port_proxy.hh"
576019Shines@cs.fsu.edu
586019Shines@cs.fsu.eduusing namespace std;
596019Shines@cs.fsu.eduusing namespace ArmISA;
606019Shines@cs.fsu.edu
616019Shines@cs.fsu.eduAddr
626019Shines@cs.fsu.eduArmISA::vtophys(Addr vaddr)
636019Shines@cs.fsu.edu{
647694SAli.Saidi@ARM.com    fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
656019Shines@cs.fsu.edu}
666019Shines@cs.fsu.edu
6710707SAndreas.Sandberg@ARM.comstatic std::pair<bool, Addr>
6810707SAndreas.Sandberg@ARM.comtry_translate(ThreadContext *tc, Addr addr)
696019Shines@cs.fsu.edu{
7010037SARM gem5 Developers    Fault fault;
7110037SARM gem5 Developers    // Set up a functional memory Request to pass to the TLB
7210037SARM gem5 Developers    // to get it to translate the vaddr to a paddr
7312749Sgiacomo.travaglini@arm.com    auto req = std::make_shared<Request>(0, addr, 64, 0x40, -1, 0, 0);
747694SAli.Saidi@ARM.com    ArmISA::TLB *tlb;
757694SAli.Saidi@ARM.com
7610037SARM gem5 Developers    // Check the TLBs for a translation
7710037SARM gem5 Developers    // It's possible that there is a valid translation in the tlb
787694SAli.Saidi@ARM.com    // that is no loger valid in the page table in memory
797694SAli.Saidi@ARM.com    // so we need to check here first
8010037SARM gem5 Developers    //
8110037SARM gem5 Developers    // Calling translateFunctional invokes a table-walk if required
8210037SARM gem5 Developers    // so we should always succeed
837694SAli.Saidi@ARM.com    tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
8412749Sgiacomo.travaglini@arm.com    fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
8510037SARM gem5 Developers    if (fault == NoFault)
8612749Sgiacomo.travaglini@arm.com        return std::make_pair(true, req->getPaddr());
877694SAli.Saidi@ARM.com
887694SAli.Saidi@ARM.com    tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
8912749Sgiacomo.travaglini@arm.com    fault = tlb->translateFunctional(req, tc, BaseTLB::Read, TLB::NormalTran);
9010037SARM gem5 Developers    if (fault == NoFault)
9112749Sgiacomo.travaglini@arm.com        return std::make_pair(true, req->getPaddr());
927694SAli.Saidi@ARM.com
9310707SAndreas.Sandberg@ARM.com    return std::make_pair(false, 0);
9410707SAndreas.Sandberg@ARM.com}
9510707SAndreas.Sandberg@ARM.com
9610707SAndreas.Sandberg@ARM.comAddr
9710707SAndreas.Sandberg@ARM.comArmISA::vtophys(ThreadContext *tc, Addr addr)
9810707SAndreas.Sandberg@ARM.com{
9910707SAndreas.Sandberg@ARM.com    const std::pair<bool, Addr> translation(try_translate(tc, addr));
10010707SAndreas.Sandberg@ARM.com
10110707SAndreas.Sandberg@ARM.com    if (translation.first)
10210707SAndreas.Sandberg@ARM.com        return translation.second;
10310707SAndreas.Sandberg@ARM.com    else
10410707SAndreas.Sandberg@ARM.com        panic("Table walkers support functional accesses. We should never get here\n");
1056019Shines@cs.fsu.edu}
1066019Shines@cs.fsu.edu
1077694SAli.Saidi@ARM.combool
1087694SAli.Saidi@ARM.comArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
1097694SAli.Saidi@ARM.com{
11010707SAndreas.Sandberg@ARM.com    const std::pair<bool, Addr> translation(try_translate(tc, vaddr));
11110707SAndreas.Sandberg@ARM.com
11210707SAndreas.Sandberg@ARM.com    return translation.first;
1137694SAli.Saidi@ARM.com}
1147694SAli.Saidi@ARM.com
1157694SAli.Saidi@ARM.com
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