14997Sgblack@eecs.umich.edu/* 25417Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34997Sgblack@eecs.umich.edu * All rights reserved. 44997Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134997Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224997Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244997Sgblack@eecs.umich.edu * 254997Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264997Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274997Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284997Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294997Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304997Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314997Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324997Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334997Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344997Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354997Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364997Sgblack@eecs.umich.edu * 374997Sgblack@eecs.umich.edu * Authors: Gabe Black 384997Sgblack@eecs.umich.edu */ 394997Sgblack@eecs.umich.edu 4011793Sbrandon.potter@amd.com#include "arch/x86/tlb.hh" 4111793Sbrandon.potter@amd.com 424997Sgblack@eecs.umich.edu#include <cstring> 4310474Sandreas.hansson@arm.com#include <memory> 444997Sgblack@eecs.umich.edu 459898Sandreas@sandberg.pp.se#include "arch/generic/mmapped_ipr.hh" 4611793Sbrandon.potter@amd.com#include "arch/x86/faults.hh" 478229Snate@binkert.org#include "arch/x86/insts/microldstop.hh" 4811793Sbrandon.potter@amd.com#include "arch/x86/pagetable_walker.hh" 498229Snate@binkert.org#include "arch/x86/regs/misc.hh" 508582Sgblack@eecs.umich.edu#include "arch/x86/regs/msr.hh" 515149Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 525086Sgblack@eecs.umich.edu#include "base/trace.hh" 535086Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 548232Snate@binkert.org#include "debug/TLB.hh" 558767Sgblack@eecs.umich.edu#include "mem/page_table.hh" 565086Sgblack@eecs.umich.edu#include "mem/request.hh" 578767Sgblack@eecs.umich.edu#include "sim/full_system.hh" 585895Sgblack@eecs.umich.edu#include "sim/process.hh" 595086Sgblack@eecs.umich.edu 605086Sgblack@eecs.umich.edunamespace X86ISA { 615086Sgblack@eecs.umich.edu 6210905Sandreas.sandberg@arm.comTLB::TLB(const Params *p) 6310905Sandreas.sandberg@arm.com : BaseTLB(p), configAddress(0), size(p->size), 6410905Sandreas.sandberg@arm.com tlb(size), lruSeq(0) 655124Sgblack@eecs.umich.edu{ 668953Sgblack@eecs.umich.edu if (!size) 678953Sgblack@eecs.umich.edu fatal("TLBs must have a non-zero size.\n"); 685124Sgblack@eecs.umich.edu 698953Sgblack@eecs.umich.edu for (int x = 0; x < size; x++) { 708953Sgblack@eecs.umich.edu tlb[x].trieHandle = NULL; 715124Sgblack@eecs.umich.edu freeList.push_back(&tlb[x]); 728953Sgblack@eecs.umich.edu } 735124Sgblack@eecs.umich.edu 745245Sgblack@eecs.umich.edu walker = p->walker; 755245Sgblack@eecs.umich.edu walker->setTLB(this); 765236Sgblack@eecs.umich.edu} 775236Sgblack@eecs.umich.edu 788953Sgblack@eecs.umich.eduvoid 798953Sgblack@eecs.umich.eduTLB::evictLRU() 808953Sgblack@eecs.umich.edu{ 818953Sgblack@eecs.umich.edu // Find the entry with the lowest (and hence least recently updated) 828953Sgblack@eecs.umich.edu // sequence number. 838953Sgblack@eecs.umich.edu 848953Sgblack@eecs.umich.edu unsigned lru = 0; 858953Sgblack@eecs.umich.edu for (unsigned i = 1; i < size; i++) { 868953Sgblack@eecs.umich.edu if (tlb[i].lruSeq < tlb[lru].lruSeq) 878953Sgblack@eecs.umich.edu lru = i; 888953Sgblack@eecs.umich.edu } 898953Sgblack@eecs.umich.edu 908953Sgblack@eecs.umich.edu assert(tlb[lru].trieHandle); 918953Sgblack@eecs.umich.edu trie.remove(tlb[lru].trieHandle); 928953Sgblack@eecs.umich.edu tlb[lru].trieHandle = NULL; 938953Sgblack@eecs.umich.edu freeList.push_back(&tlb[lru]); 948953Sgblack@eecs.umich.edu} 958953Sgblack@eecs.umich.edu 965895Sgblack@eecs.umich.eduTlbEntry * 9712455Sgabeblack@google.comTLB::insert(Addr vpn, const TlbEntry &entry) 985124Sgblack@eecs.umich.edu{ 998962Sgblack@eecs.umich.edu // If somebody beat us to it, just use that existing entry. 1008962Sgblack@eecs.umich.edu TlbEntry *newEntry = trie.lookup(vpn); 1018962Sgblack@eecs.umich.edu if (newEntry) { 1029064Snilay@cs.wisc.edu assert(newEntry->vaddr == vpn); 1038962Sgblack@eecs.umich.edu return newEntry; 1048962Sgblack@eecs.umich.edu } 1055124Sgblack@eecs.umich.edu 1068953Sgblack@eecs.umich.edu if (freeList.empty()) 1078953Sgblack@eecs.umich.edu evictLRU(); 1088962Sgblack@eecs.umich.edu 1098953Sgblack@eecs.umich.edu newEntry = freeList.front(); 1108953Sgblack@eecs.umich.edu freeList.pop_front(); 1118953Sgblack@eecs.umich.edu 1125124Sgblack@eecs.umich.edu *newEntry = entry; 1138953Sgblack@eecs.umich.edu newEntry->lruSeq = nextSeq(); 1145124Sgblack@eecs.umich.edu newEntry->vaddr = vpn; 1158953Sgblack@eecs.umich.edu newEntry->trieHandle = 1168962Sgblack@eecs.umich.edu trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 1175895Sgblack@eecs.umich.edu return newEntry; 1185124Sgblack@eecs.umich.edu} 1195124Sgblack@eecs.umich.edu 1205360Sgblack@eecs.umich.eduTlbEntry * 1215360Sgblack@eecs.umich.eduTLB::lookup(Addr va, bool update_lru) 1225360Sgblack@eecs.umich.edu{ 1238953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1248953Sgblack@eecs.umich.edu if (entry && update_lru) 1258953Sgblack@eecs.umich.edu entry->lruSeq = nextSeq(); 1268953Sgblack@eecs.umich.edu return entry; 1275124Sgblack@eecs.umich.edu} 1285124Sgblack@eecs.umich.edu 1295124Sgblack@eecs.umich.eduvoid 1309423SAndreas.Sandberg@arm.comTLB::flushAll() 1315124Sgblack@eecs.umich.edu{ 1325242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all entries.\n"); 1338953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1348953Sgblack@eecs.umich.edu if (tlb[i].trieHandle) { 1358953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1368953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1378953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1388953Sgblack@eecs.umich.edu } 1395242Sgblack@eecs.umich.edu } 1405124Sgblack@eecs.umich.edu} 1415124Sgblack@eecs.umich.edu 1425124Sgblack@eecs.umich.eduvoid 1435357Sgblack@eecs.umich.eduTLB::setConfigAddress(uint32_t addr) 1445357Sgblack@eecs.umich.edu{ 1455357Sgblack@eecs.umich.edu configAddress = addr; 1465357Sgblack@eecs.umich.edu} 1475357Sgblack@eecs.umich.edu 1485357Sgblack@eecs.umich.eduvoid 1499423SAndreas.Sandberg@arm.comTLB::flushNonGlobal() 1505124Sgblack@eecs.umich.edu{ 1515242Sgblack@eecs.umich.edu DPRINTF(TLB, "Invalidating all non global entries.\n"); 1528953Sgblack@eecs.umich.edu for (unsigned i = 0; i < size; i++) { 1538953Sgblack@eecs.umich.edu if (tlb[i].trieHandle && !tlb[i].global) { 1548953Sgblack@eecs.umich.edu trie.remove(tlb[i].trieHandle); 1558953Sgblack@eecs.umich.edu tlb[i].trieHandle = NULL; 1568953Sgblack@eecs.umich.edu freeList.push_back(&tlb[i]); 1575242Sgblack@eecs.umich.edu } 1585242Sgblack@eecs.umich.edu } 1595124Sgblack@eecs.umich.edu} 1605124Sgblack@eecs.umich.edu 1615124Sgblack@eecs.umich.eduvoid 1625358Sgblack@eecs.umich.eduTLB::demapPage(Addr va, uint64_t asn) 1635086Sgblack@eecs.umich.edu{ 1648953Sgblack@eecs.umich.edu TlbEntry *entry = trie.lookup(va); 1658953Sgblack@eecs.umich.edu if (entry) { 1668953Sgblack@eecs.umich.edu trie.remove(entry->trieHandle); 1678953Sgblack@eecs.umich.edu entry->trieHandle = NULL; 1688953Sgblack@eecs.umich.edu freeList.push_back(entry); 1695359Sgblack@eecs.umich.edu } 1705086Sgblack@eecs.umich.edu} 1715086Sgblack@eecs.umich.edu 1725086Sgblack@eecs.umich.eduFault 17312749Sgiacomo.travaglini@arm.comTLB::translateInt(const RequestPtr &req, ThreadContext *tc) 1746141Sgblack@eecs.umich.edu{ 1756141Sgblack@eecs.umich.edu DPRINTF(TLB, "Addresses references internal memory.\n"); 1766141Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 1776141Sgblack@eecs.umich.edu Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 1786141Sgblack@eecs.umich.edu if (prefix == IntAddrPrefixCPUID) { 1796141Sgblack@eecs.umich.edu panic("CPUID memory space not yet implemented!\n"); 1806141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixMSR) { 1818582Sgblack@eecs.umich.edu vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 1828105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 1838582Sgblack@eecs.umich.edu 1848582Sgblack@eecs.umich.edu MiscRegIndex regNum; 1858582Sgblack@eecs.umich.edu if (!msrAddrToIndex(regNum, vaddr)) 18610474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 1878582Sgblack@eecs.umich.edu 18813613Sgabeblack@google.com //The index is multiplied by the size of a RegVal so that 1896141Sgblack@eecs.umich.edu //any memory dependence calculations will not see these as 1906141Sgblack@eecs.umich.edu //overlapping. 19113613Sgabeblack@google.com req->setPaddr((Addr)regNum * sizeof(RegVal)); 1926141Sgblack@eecs.umich.edu return NoFault; 1936141Sgblack@eecs.umich.edu } else if (prefix == IntAddrPrefixIO) { 1946141Sgblack@eecs.umich.edu // TODO If CPL > IOPL or in virtual mode, check the I/O permission 1956141Sgblack@eecs.umich.edu // bitmap in the TSS. 1966141Sgblack@eecs.umich.edu 1976141Sgblack@eecs.umich.edu Addr IOPort = vaddr & ~IntAddrPrefixMask; 1986141Sgblack@eecs.umich.edu // Make sure the address fits in the expected 16 bit IO address 1996141Sgblack@eecs.umich.edu // space. 2006141Sgblack@eecs.umich.edu assert(!(IOPort & ~0xFFFF)); 2016141Sgblack@eecs.umich.edu if (IOPort == 0xCF8 && req->getSize() == 4) { 2028105Sgblack@eecs.umich.edu req->setFlags(Request::MMAPPED_IPR); 20313613Sgabeblack@google.com req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal)); 2046141Sgblack@eecs.umich.edu } else if ((IOPort & ~mask(2)) == 0xCFC) { 20510824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2066141Sgblack@eecs.umich.edu Addr configAddress = 2076141Sgblack@eecs.umich.edu tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 2086141Sgblack@eecs.umich.edu if (bits(configAddress, 31, 31)) { 2096141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixPciConfig | 2106141Sgblack@eecs.umich.edu mbits(configAddress, 30, 2) | 2116141Sgblack@eecs.umich.edu (IOPort & mask(2))); 2128098Sgblack@eecs.umich.edu } else { 2138098Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2146141Sgblack@eecs.umich.edu } 2156141Sgblack@eecs.umich.edu } else { 21610824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2176141Sgblack@eecs.umich.edu req->setPaddr(PhysAddrPrefixIO | IOPort); 2186141Sgblack@eecs.umich.edu } 2196141Sgblack@eecs.umich.edu return NoFault; 2206141Sgblack@eecs.umich.edu } else { 2216141Sgblack@eecs.umich.edu panic("Access to unrecognized internal address space %#x.\n", 2226141Sgblack@eecs.umich.edu prefix); 2236141Sgblack@eecs.umich.edu } 2246141Sgblack@eecs.umich.edu} 2256141Sgblack@eecs.umich.edu 2266141Sgblack@eecs.umich.eduFault 22712749Sgiacomo.travaglini@arm.comTLB::finalizePhysical(const RequestPtr &req, 22812749Sgiacomo.travaglini@arm.com ThreadContext *tc, Mode mode) const 2299738Sandreas@sandberg.pp.se{ 2309738Sandreas@sandberg.pp.se Addr paddr = req->getPaddr(); 2319738Sandreas@sandberg.pp.se 23210553Salexandru.dutu@amd.com AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF); 23310553Salexandru.dutu@amd.com 23410553Salexandru.dutu@amd.com if (m5opRange.contains(paddr)) { 23511874Sbrandon.potter@amd.com req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR | 23611874Sbrandon.potter@amd.com Request::STRICT_ORDER); 23711874Sbrandon.potter@amd.com req->setPaddr(GenericISA::iprAddressPseudoInst((paddr >> 8) & 0xFF, 23811874Sbrandon.potter@amd.com paddr & 0xFF)); 23910553Salexandru.dutu@amd.com } else if (FullSystem) { 24010553Salexandru.dutu@amd.com // Check for an access to the local APIC 2419738Sandreas@sandberg.pp.se LocalApicBase localApicBase = 2429738Sandreas@sandberg.pp.se tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 2439738Sandreas@sandberg.pp.se AddrRange apicRange(localApicBase.base * PageBytes, 2449738Sandreas@sandberg.pp.se (localApicBase.base + 1) * PageBytes - 1); 2459738Sandreas@sandberg.pp.se 2469738Sandreas@sandberg.pp.se if (apicRange.contains(paddr)) { 2479738Sandreas@sandberg.pp.se // The Intel developer's manuals say the below restrictions apply, 2489738Sandreas@sandberg.pp.se // but the linux kernel, because of a compiler optimization, breaks 2499738Sandreas@sandberg.pp.se // them. 2509738Sandreas@sandberg.pp.se /* 2519738Sandreas@sandberg.pp.se // Check alignment 2529738Sandreas@sandberg.pp.se if (paddr & ((32/8) - 1)) 2539738Sandreas@sandberg.pp.se return new GeneralProtection(0); 2549738Sandreas@sandberg.pp.se // Check access size 2559738Sandreas@sandberg.pp.se if (req->getSize() != (32/8)) 2569738Sandreas@sandberg.pp.se return new GeneralProtection(0); 2579738Sandreas@sandberg.pp.se */ 2589738Sandreas@sandberg.pp.se // Force the access to be uncacheable. 25910824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 2609738Sandreas@sandberg.pp.se req->setPaddr(x86LocalAPICAddress(tc->contextId(), 2619738Sandreas@sandberg.pp.se paddr - apicRange.start())); 2629738Sandreas@sandberg.pp.se } 2639738Sandreas@sandberg.pp.se } 2649738Sandreas@sandberg.pp.se 2659738Sandreas@sandberg.pp.se return NoFault; 2669738Sandreas@sandberg.pp.se} 2679738Sandreas@sandberg.pp.se 2689738Sandreas@sandberg.pp.seFault 26912749Sgiacomo.travaglini@arm.comTLB::translate(const RequestPtr &req, 27012749Sgiacomo.travaglini@arm.com ThreadContext *tc, Translation *translation, 2716023Snate@binkert.org Mode mode, bool &delayedResponse, bool timing) 2725086Sgblack@eecs.umich.edu{ 27311608Snikos.nikoleris@arm.com Request::Flags flags = req->getFlags(); 2746141Sgblack@eecs.umich.edu int seg = flags & SegmentFlagMask; 2756141Sgblack@eecs.umich.edu bool storeCheck = flags & (StoreCheck << FlagShift); 2766141Sgblack@eecs.umich.edu 2778535Sgblack@eecs.umich.edu delayedResponse = false; 2788535Sgblack@eecs.umich.edu 2796141Sgblack@eecs.umich.edu // If this is true, we're dealing with a request to a non-memory address 2806141Sgblack@eecs.umich.edu // space. 2816141Sgblack@eecs.umich.edu if (seg == SEGMENT_REG_MS) { 2826141Sgblack@eecs.umich.edu return translateInt(req, tc); 2836141Sgblack@eecs.umich.edu } 2846141Sgblack@eecs.umich.edu 2855124Sgblack@eecs.umich.edu Addr vaddr = req->getVaddr(); 2865140Sgblack@eecs.umich.edu DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 2875140Sgblack@eecs.umich.edu 2886141Sgblack@eecs.umich.edu HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 2895140Sgblack@eecs.umich.edu 2905140Sgblack@eecs.umich.edu // If protected mode has been enabled... 2916141Sgblack@eecs.umich.edu if (m5Reg.prot) { 2925237Sgblack@eecs.umich.edu DPRINTF(TLB, "In protected mode.\n"); 2935140Sgblack@eecs.umich.edu // If we're not in 64-bit mode, do protection/limit checks 2946141Sgblack@eecs.umich.edu if (m5Reg.mode != LongMode) { 2955237Sgblack@eecs.umich.edu DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 2965431Sgblack@eecs.umich.edu // Check for a NULL segment selector. 2976059Sgblack@eecs.umich.edu if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 2986141Sgblack@eecs.umich.edu seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 2996059Sgblack@eecs.umich.edu && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 30010474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3015433Sgblack@eecs.umich.edu bool expandDown = false; 3025965Sgblack@eecs.umich.edu SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 3035433Sgblack@eecs.umich.edu if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 3046099Sgblack@eecs.umich.edu if (!attr.writable && (mode == Write || storeCheck)) 30510474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3066023Snate@binkert.org if (!attr.readable && mode == Read) 30710474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3085433Sgblack@eecs.umich.edu expandDown = attr.expandDown; 3095965Sgblack@eecs.umich.edu 3105433Sgblack@eecs.umich.edu } 3115140Sgblack@eecs.umich.edu Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 3125140Sgblack@eecs.umich.edu Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 3135965Sgblack@eecs.umich.edu bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 3149062Sjayneel@cs.wisc.edu unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 3159062Sjayneel@cs.wisc.edu : (unsigned)m5Reg.defAddr; 3169028Sgblack@eecs.umich.edu int size = (1 << logSize) * 8; 3179028Sgblack@eecs.umich.edu Addr offset = bits(vaddr - base, size - 1, 0); 3185965Sgblack@eecs.umich.edu Addr endOffset = offset + req->getSize() - 1; 3195433Sgblack@eecs.umich.edu if (expandDown) { 3205237Sgblack@eecs.umich.edu DPRINTF(TLB, "Checking an expand down segment.\n"); 3215965Sgblack@eecs.umich.edu warn_once("Expand down segments are untested.\n"); 3225965Sgblack@eecs.umich.edu if (offset <= limit || endOffset <= limit) 32310474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3245140Sgblack@eecs.umich.edu } else { 3255965Sgblack@eecs.umich.edu if (offset > limit || endOffset > limit) 32610474Sandreas.hansson@arm.com return std::make_shared<GeneralProtection>(0); 3275140Sgblack@eecs.umich.edu } 3285140Sgblack@eecs.umich.edu } 3299025Sgblack@eecs.umich.edu if (m5Reg.submode != SixtyFourBitMode || 3308925Sgblack@eecs.umich.edu (flags & (AddrSizeFlagBit << FlagShift))) 3318925Sgblack@eecs.umich.edu vaddr &= mask(32); 3325140Sgblack@eecs.umich.edu // If paging is enabled, do the translation. 3336141Sgblack@eecs.umich.edu if (m5Reg.paging) { 3345237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging enabled.\n"); 3355140Sgblack@eecs.umich.edu // The vaddr already has the segment base applied. 3365140Sgblack@eecs.umich.edu TlbEntry *entry = lookup(vaddr); 33712140Sswapnilster@gmail.com if (mode == Read) { 33812140Sswapnilster@gmail.com rdAccesses++; 33912140Sswapnilster@gmail.com } else { 34012140Sswapnilster@gmail.com wrAccesses++; 34112140Sswapnilster@gmail.com } 3425140Sgblack@eecs.umich.edu if (!entry) { 34312140Sswapnilster@gmail.com DPRINTF(TLB, "Handling a TLB miss for " 34412140Sswapnilster@gmail.com "address %#x at pc %#x.\n", 34512140Sswapnilster@gmail.com vaddr, tc->instAddr()); 34612140Sswapnilster@gmail.com if (mode == Read) { 34712140Sswapnilster@gmail.com rdMisses++; 34812140Sswapnilster@gmail.com } else { 34912140Sswapnilster@gmail.com wrMisses++; 35012140Sswapnilster@gmail.com } 3518752Sgblack@eecs.umich.edu if (FullSystem) { 3528752Sgblack@eecs.umich.edu Fault fault = walker->start(tc, translation, req, mode); 3538752Sgblack@eecs.umich.edu if (timing || fault != NoFault) { 3548752Sgblack@eecs.umich.edu // This gets ignored in atomic mode. 3558752Sgblack@eecs.umich.edu delayedResponse = true; 3568752Sgblack@eecs.umich.edu return fault; 3578752Sgblack@eecs.umich.edu } 3588752Sgblack@eecs.umich.edu entry = lookup(vaddr); 3598752Sgblack@eecs.umich.edu assert(entry); 3608752Sgblack@eecs.umich.edu } else { 3618752Sgblack@eecs.umich.edu Process *p = tc->getProcessPtr(); 36212461Sgabeblack@google.com const EmulationPageTable::Entry *pte = 36312461Sgabeblack@google.com p->pTable->lookup(vaddr); 36412461Sgabeblack@google.com if (!pte && mode != Execute) { 3658752Sgblack@eecs.umich.edu // Check if we just need to grow the stack. 3668752Sgblack@eecs.umich.edu if (p->fixupStackFault(vaddr)) { 3678752Sgblack@eecs.umich.edu // If we did, lookup the entry for the new page. 36812461Sgabeblack@google.com pte = p->pTable->lookup(vaddr); 3698752Sgblack@eecs.umich.edu } 3708752Sgblack@eecs.umich.edu } 37112461Sgabeblack@google.com if (!pte) { 37210474Sandreas.hansson@arm.com return std::make_shared<PageFault>(vaddr, true, mode, 37310474Sandreas.hansson@arm.com true, false); 3748752Sgblack@eecs.umich.edu } else { 3758752Sgblack@eecs.umich.edu Addr alignedVaddr = p->pTable->pageAlign(vaddr); 3768752Sgblack@eecs.umich.edu DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 37712461Sgabeblack@google.com pte->paddr); 37812461Sgabeblack@google.com entry = insert(alignedVaddr, TlbEntry( 37912461Sgabeblack@google.com p->pTable->pid(), alignedVaddr, pte->paddr, 38012461Sgabeblack@google.com pte->flags & EmulationPageTable::Uncacheable, 38112461Sgabeblack@google.com pte->flags & EmulationPageTable::ReadOnly)); 3828752Sgblack@eecs.umich.edu } 3838752Sgblack@eecs.umich.edu DPRINTF(TLB, "Miss was serviced.\n"); 3845895Sgblack@eecs.umich.edu } 3855140Sgblack@eecs.umich.edu } 3868646Snilay@cs.wisc.edu 3878646Snilay@cs.wisc.edu DPRINTF(TLB, "Entry found with paddr %#x, " 3888646Snilay@cs.wisc.edu "doing protection checks.\n", entry->paddr); 3895895Sgblack@eecs.umich.edu // Do paging protection checks. 3906141Sgblack@eecs.umich.edu bool inUser = (m5Reg.cpl == 3 && 3915917Sgblack@eecs.umich.edu !(flags & (CPL0FlagBit << FlagShift))); 3927933Stharris@microsoft.com CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 3937933Stharris@microsoft.com bool badWrite = (!entry->writable && (inUser || cr0.wp)); 3947933Stharris@microsoft.com if ((inUser && !entry->user) || (mode == Write && badWrite)) { 3955917Sgblack@eecs.umich.edu // The page must have been present to get into the TLB in 3965917Sgblack@eecs.umich.edu // the first place. We'll assume the reserved bits are 3975917Sgblack@eecs.umich.edu // fine even though we're not checking them. 39810474Sandreas.hansson@arm.com return std::make_shared<PageFault>(vaddr, true, mode, inUser, 39910474Sandreas.hansson@arm.com false); 4005917Sgblack@eecs.umich.edu } 4017933Stharris@microsoft.com if (storeCheck && badWrite) { 4026099Sgblack@eecs.umich.edu // This would fault if this were a write, so return a page 4036099Sgblack@eecs.umich.edu // fault that reflects that happening. 40410474Sandreas.hansson@arm.com return std::make_shared<PageFault>(vaddr, true, Write, inUser, 40510474Sandreas.hansson@arm.com false); 4066099Sgblack@eecs.umich.edu } 4075917Sgblack@eecs.umich.edu 4088953Sgblack@eecs.umich.edu Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 4095895Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 4105895Sgblack@eecs.umich.edu req->setPaddr(paddr); 4117775Sgblack@eecs.umich.edu if (entry->uncacheable) 41210824SAndreas.Sandberg@ARM.com req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); 4135140Sgblack@eecs.umich.edu } else { 4145140Sgblack@eecs.umich.edu //Use the address which already has segmentation applied. 4155237Sgblack@eecs.umich.edu DPRINTF(TLB, "Paging disabled.\n"); 4165237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 4175140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 4185140Sgblack@eecs.umich.edu } 4195124Sgblack@eecs.umich.edu } else { 4205140Sgblack@eecs.umich.edu // Real mode 4215237Sgblack@eecs.umich.edu DPRINTF(TLB, "In real mode.\n"); 4225237Sgblack@eecs.umich.edu DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 4235140Sgblack@eecs.umich.edu req->setPaddr(vaddr); 4245124Sgblack@eecs.umich.edu } 4259738Sandreas@sandberg.pp.se 4269738Sandreas@sandberg.pp.se return finalizePhysical(req, tc, mode); 4278902Sandreas.hansson@arm.com} 4285086Sgblack@eecs.umich.edu 4295140Sgblack@eecs.umich.eduFault 43012749Sgiacomo.travaglini@arm.comTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 4315140Sgblack@eecs.umich.edu{ 4325895Sgblack@eecs.umich.edu bool delayedResponse; 4336023Snate@binkert.org return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 4345140Sgblack@eecs.umich.edu} 4355140Sgblack@eecs.umich.edu 4365894Sgblack@eecs.umich.eduvoid 43712749Sgiacomo.travaglini@arm.comTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, 4386023Snate@binkert.org Translation *translation, Mode mode) 4395894Sgblack@eecs.umich.edu{ 4405895Sgblack@eecs.umich.edu bool delayedResponse; 4415894Sgblack@eecs.umich.edu assert(translation); 4426023Snate@binkert.org Fault fault = 4436023Snate@binkert.org TLB::translate(req, tc, translation, mode, delayedResponse, true); 4445895Sgblack@eecs.umich.edu if (!delayedResponse) 4456023Snate@binkert.org translation->finish(fault, req, tc, mode); 44613937Sgabor.dozsa@arm.com else 44713937Sgabor.dozsa@arm.com translation->markDelayed(); 4485894Sgblack@eecs.umich.edu} 4495894Sgblack@eecs.umich.edu 4507912Shestness@cs.utexas.eduWalker * 4517912Shestness@cs.utexas.eduTLB::getWalker() 4527912Shestness@cs.utexas.edu{ 4537912Shestness@cs.utexas.edu return walker; 4547912Shestness@cs.utexas.edu} 4557912Shestness@cs.utexas.edu 4565086Sgblack@eecs.umich.eduvoid 45712140Sswapnilster@gmail.comTLB::regStats() 45812140Sswapnilster@gmail.com{ 45912140Sswapnilster@gmail.com using namespace Stats; 46013695Shanindhito@bagus.my.id BaseTLB::regStats(); 46112140Sswapnilster@gmail.com rdAccesses 46212140Sswapnilster@gmail.com .name(name() + ".rdAccesses") 46312140Sswapnilster@gmail.com .desc("TLB accesses on read requests"); 46412140Sswapnilster@gmail.com 46512140Sswapnilster@gmail.com wrAccesses 46612140Sswapnilster@gmail.com .name(name() + ".wrAccesses") 46712140Sswapnilster@gmail.com .desc("TLB accesses on write requests"); 46812140Sswapnilster@gmail.com 46912140Sswapnilster@gmail.com rdMisses 47012140Sswapnilster@gmail.com .name(name() + ".rdMisses") 47112140Sswapnilster@gmail.com .desc("TLB misses on read requests"); 47212140Sswapnilster@gmail.com 47312140Sswapnilster@gmail.com wrMisses 47412140Sswapnilster@gmail.com .name(name() + ".wrMisses") 47512140Sswapnilster@gmail.com .desc("TLB misses on write requests"); 47612140Sswapnilster@gmail.com 47712140Sswapnilster@gmail.com} 47812140Sswapnilster@gmail.com 47912140Sswapnilster@gmail.comvoid 48010905Sandreas.sandberg@arm.comTLB::serialize(CheckpointOut &cp) const 4815086Sgblack@eecs.umich.edu{ 4829818Snilay@cs.wisc.edu // Only store the entries in use. 4839818Snilay@cs.wisc.edu uint32_t _size = size - freeList.size(); 4849818Snilay@cs.wisc.edu SERIALIZE_SCALAR(_size); 4859818Snilay@cs.wisc.edu SERIALIZE_SCALAR(lruSeq); 4869818Snilay@cs.wisc.edu 4879818Snilay@cs.wisc.edu uint32_t _count = 0; 4889818Snilay@cs.wisc.edu for (uint32_t x = 0; x < size; x++) { 48910905Sandreas.sandberg@arm.com if (tlb[x].trieHandle != NULL) 49010905Sandreas.sandberg@arm.com tlb[x].serializeSection(cp, csprintf("Entry%d", _count++)); 4919818Snilay@cs.wisc.edu } 4925086Sgblack@eecs.umich.edu} 4935086Sgblack@eecs.umich.edu 4945086Sgblack@eecs.umich.eduvoid 49510905Sandreas.sandberg@arm.comTLB::unserialize(CheckpointIn &cp) 4965086Sgblack@eecs.umich.edu{ 4979818Snilay@cs.wisc.edu // Do not allow to restore with a smaller tlb. 4989818Snilay@cs.wisc.edu uint32_t _size; 4999818Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(_size); 5009818Snilay@cs.wisc.edu if (_size > size) { 5019818Snilay@cs.wisc.edu fatal("TLB size less than the one in checkpoint!"); 5029818Snilay@cs.wisc.edu } 5039818Snilay@cs.wisc.edu 5049818Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(lruSeq); 5059818Snilay@cs.wisc.edu 5069818Snilay@cs.wisc.edu for (uint32_t x = 0; x < _size; x++) { 5079818Snilay@cs.wisc.edu TlbEntry *newEntry = freeList.front(); 5089818Snilay@cs.wisc.edu freeList.pop_front(); 5099818Snilay@cs.wisc.edu 51010905Sandreas.sandberg@arm.com newEntry->unserializeSection(cp, csprintf("Entry%d", x)); 5119818Snilay@cs.wisc.edu newEntry->trieHandle = trie.insert(newEntry->vaddr, 5129818Snilay@cs.wisc.edu TlbEntryTrie::MaxBits - newEntry->logBytes, newEntry); 5139818Snilay@cs.wisc.edu } 5145086Sgblack@eecs.umich.edu} 5155086Sgblack@eecs.umich.edu 51613784Sgabeblack@google.comPort * 51713784Sgabeblack@google.comTLB::getTableWalkerPort() 5188864Snilay@cs.wisc.edu{ 51913784Sgabeblack@google.com return &walker->getPort("port"); 5208864Snilay@cs.wisc.edu} 5218864Snilay@cs.wisc.edu 5227811Ssteve.reinhardt@amd.com} // namespace X86ISA 5235086Sgblack@eecs.umich.edu 5246022Sgblack@eecs.umich.eduX86ISA::TLB * 5256022Sgblack@eecs.umich.eduX86TLBParams::create() 5264997Sgblack@eecs.umich.edu{ 5276022Sgblack@eecs.umich.edu return new X86ISA::TLB(this); 5284997Sgblack@eecs.umich.edu} 529